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[802.3_100GCU] ad-hoc meeting 10/11/2012 meeting notes



802.3bj PAM4 Interference Tolerance PAM4
2012 October 11:  1200 MDT
Attendees:
Adam Healey              LSI
Adee Ran                 Intel
Ali Ghiasi               Broadcom
Alexander Umnov          Huawei
Charles Moore            Avago
Chung-jue Chen           Broadcom
Elizabeth Kochuparambil  Cisco
Galen Fromm              Cray
Jeff Slavick             Avago
Matthew Brown            APM
Megha Shanbhag           TE
Mike Dudek               QLogic
Mike Li                  Altera
Pavel Zivny              Tektronix
Rich Mellitz             Intel
Vasudevan Parthasarathy  Broadcom
Vittal Balasubramanian   Brocade
Wheling Cheng            Juniper
Will Bliss               Broadcom
Zhongfeng Wang           Broadcom


Notes thanks to Jeff Slavic.

Duration ~90min

Asked if anyone is not familiar with the patent policy of IEEE?

No responses

Reviewed the 100G Basekp4 Interference tolerance ad hoc slides

               Slide 3

               Option 1 not viable, since it was turned down in Sept
Interim

               Option 2 not viable, since it relies on qikSN which is
not being used

               Option 3 look into

               Option 4 do we need to change what we specify?

Should the PMD testing be done w/o the presence of FEC?

               No consensus

Slide 4 - Option 3

               Do we need to stress the voltage and timing in two
separate tests?

Option 4

               Do you need to test the system as a whole?  Since that
is the environment that you’re running in, otherwise you have to add
more testing to validate with FEC enabled.  Should we validate with FEC?


Do we want to remove the Max BER w/o FEC from Table 94-7 since it’s
always present?  Depends on if we can test with FEC data streams or not.


Need to define tests for:

               Ability to receive data assuming proper timing, vertical
stress.

               Check the CDR operation, horizontal stress.

Suggestion create 2 tests:

1)      Jitter tolerance test – no voltage stressing, validate SJ
tolerance, high amplitude, low frequency

2)      Interference test -  includes some SJ @ high freuqency

Back in ap days we had long discussions and the result was that we should:

Assume WC transmitter and WC channel.  Which includes low & high
frequency jitter and WC channels includes high interference.



Can the view of the Rx tesing be done with:

2 COM values

1)      Interconnect

2)      Rx tolerance value



How do you define the WC Tx and WC channel?  COM is comprised of
multiple inputs, so you have to bound both COM and values.

How do you cover this with minimal tests?   What is independent and
correlated or orthogonal?

Do we assume that Tx COM is WC always?

Suggestion

Should we specify it as target COM at Rx input.   The delta between test
COM and WC channel is the Tx COM  + noise + test setup + jitter + etc.

Ceate N tests that all have the same COM at the Rx input.   Build up the
tests to reach that COM level using each of the WC values.   Need to
make sure it’s feasible to build it.

                               High Atten channel

                               High RJ

                               Short channel + DJ

                               Channel + Vert noise


Adi ‘s thoughts emailed to group of attendees in this file:  *RX
tolerance ad-hoc initial ideas.pptx    *

               Integrate channel spec (COM) into Rx tolerance tests

               Propose that the JTOL is handled separately

               Loss:  2 cases  one low, one high

               COM:   Up the COM to meet the target by adding in other
sources of interference

               Jitter:  low and high frequency, 2 tests

               SNDR: of the transmitter can be calculated, compensated
with noise if not WC


Pattgen w/ FEC???  How do we get this?

Since we’re not a perfect world, how do you create the perfect with
imperfection until perfection is available?

Instruments would be required to supply FEC data + 90/92 frame markers.
To do a post FEC testing, need to have instrument that transmit data out
4 lane.   Pattern would need to be 5440 / 2 long if that repeats
uniformly over 4 lanes and we can send RAMs, otherwise it’s way too
between AMs.



Can we use Annex 69A?   Matt thinks that we’ll have to rewrite Annex 69A
and create an Annex 94.X.  May have to overhaul Annex 69A for 93A.



Action items:

1.  Define a pattern used for PAM4 to be used for testing of the Rx, and
determine if it’s feasible for current equipment to supply the
pattern.   Will Bliss will take this on.  Pavel will help Will
understand the capabilities of the equipment.   Due date of 10/25/2012
ad-hoc meeting.

2.  Group will try to get email dialog going for driving some of the
solutions.

3. Charles supply minutes and list of attendees

4. Adi to expand on his presentation, look at adding a version of Table
94-7.



Next meeting:   10/25/2012 for 90min @noon Mountain Time.