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This is a follow up to last Wednesday’s Ad hoc (3/31/21). Let’s start a dialog to discuss this. If needed perhaps we can have quick meeting to discuss. The attached pdf includes a suggestion for adding jitter specifications to module/host outputs and refining jitter injection to align to receiver test point inputs. In addition, there is a suggestion for ADD which may align better to measurements using C2M simulation which estimate VEC/EH (using COM etc). Best Regards, Richard Mellitz Samtec -----Original Appointment----- Request for presentation time is the Monday prior to each of these meetings and presentations will be due Noon PDT on that Tuesday (the day before the ad hoc). The request for presentation should include: author(s), title, brief summary, and time requested including Q&A. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Join the meeting with your name and affiliation listed in the Webex participation list; you’ll need to input this before you enter the meeting. And please be familiar with IEEE policies prior to the call: IEEE patent policy - http://www.ieee802.org/3/patent.html and http://standards.ieee.org/about/sasb/patcom/materials.html Participant policy - http://www.ieee802.org/devdocs.shtml Copyright policy - https://standards.ieee.org/ipr/index.html
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Attachment:
Chip to Module p3ck d2p0 proposals.pdf
Description: Adobe PDF document