Thread Links Date Links
Thread Prev Thread Next Thread Index Date Prev Date Next Date Index

Re: XGMII electricals




Bob,

I can't agree with you more. I took issue with the same decisions over
this reflector soon after the New Orleans meeting. We need a resolution
to this issue very soon. You've already listed most of the possible
resolutions in your original note. I feel very uncomfortable with (3)
which in essence requires the development of a brand new interface spec
for an interface which will likely be integrated very quickly. If I may,
I'd like to suggest an alternative resolution, call it #4:

4.  Allow XGMII I/O to be either SSTL or HSTL per the appropriate EIA/
specs and selection of options thereof.

Best Regards,
Rich
     
--

"Grow, Bob" wrote:
> 
> Implementing the XGMII concensus of the Task Force expressed through straw
> polls in New Orleans is a problem. In fact, I would characterize the actions
> we took in New Orleans to be an example of group think gone wild.  We had a
> comprehensive SSTL specification in the draft, but made the straw poll votes
> to change on concepts, not proposed specifications.
> 
> There is no standard for HSTL at 1.8 volts (the preferred voltage per straw
> poll), nor did the TF select any other parameters of the electrical
> specifications.  (Class I, 1.5 volt  HSTL as specified in EIA/JESD8-6 is the
> closest standardized alternative that the team working on clause 46 could
> find).  Because we couldn't find a standard to reference and the Task Force
> didn't endorse a complete set of 1.8 volt specifications, there was no way
> an HSTL electrical specification could be inserted into the draft without
> adding a lot of technical material that hadn't been endorsed by the
> committee.  Therefore, all you will find in Draft 1.1 on HSTL is an editor's
> note describing the situation.
> 
> Most discussion supports the idea that the XGMII electrical interface is for
> near term usage (with continued use as an module to module logic interface
> within a chip). Implemeters expect the electrical interface to be supported
> by I/O devices in quick turn silicon libraries.  Some participants in the
> editorial session thought ASIC vendors might have a 1.8 volt HSTL derived
> from the above referenced specification, but weren't sure of any vendors
> supporting it (for inclusion in the standard it should be supported by many
> vendors).
> 
> We have a similar problem with the clock alignment were the straw poll
> endorsed a change without any specifications to implement the change (e.g.,
> skew specifications).
> 
> As it now stands, I would vote against going to Task Force ballot.  It would
> be a shame for TF ballot to be delayed because of the absence of XGMII
> electricals.  I see three alternatives that would allow us to go forward to
> TF ballot.
> 
> 1.  Return to the SSTL specifications of Draft 1.0
> 2.  Reference HSTL at 1.5 volts per EIA/JESD8-6 and select from the options
> within that specification.
> 3.  Someone presents a detailed proposal including all appropriate
> specifications (timing, thresholds, AC and DC characteristics, termination,
> etc.)
> 
> As the clause editor, I will be proposing alternative 1 in Tampa unless
> participants come through with presentations (sufficiently detailed to go to
> TF ballot), and the Task Force endorses the specifications presented.
> 
> Bob Grow
> Editor Clause 46
                                 
------------------------------------------------------- 
Richard Taborek Sr.                 Phone: 408-845-6102       
Chief Technology Officer             Cell: 408-832-3957
nSerial Corporation                   Fax: 408-845-6114
2500-5 Augustine Dr.        mailto:rtaborek@xxxxxxxxxxx
Santa Clara, CA 95054            http://www.nSerial.com