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Re: 64/66 system benefits and ad-hoc agenda


    thank you for your elaborate emails. I guess I sound a bit like devil's
advocate, but
would like to ensure you that I am not at all against scrambling, on the
What I like about the Nortel approach (Lucent had a similar presentation on a
serial link called simplified data link, SDL) is that it provides scrambling
requiring the extra 2 bits (no rate conversion). My understanding was that
there is already
enough overhead in the Ethernet packets ( for ex: in the IPG or preamble which
can be
stripped out and restored before entering the MAC), that one should be able to
a code that does not require any extra overhead. The particular scrambler
polynomial and
implementation in the Nortel proposal seems to me like an orthogonal issue. We
be able to change the scrambler scheme if necessary.

>> 5) rate conversion 64 to 66: puts some burden on the 10GHz PLL design,
>> and requires rate conversion + FIFO.
>This is always the case in a code that expands the space.  8B/10B needs
>a rate conversion.  SONET also needs similar circuitry.

8b/10b seems to be a given for Hari. If one were to keep a rate of 12.5Gb/s
there is no rate conversion. Also if the WWDM scheme is based on 8b/10b there
wouldn't be any rate conversion in the PHY.

With respect to SONET I thought typical mux designs are based on a simple 4:1
(or 16:1)
and that's the type of circuit available today. I don't see how one could map
66 bits into a
4:1 mux easily and therefore don't understand why the 64b/66b is not affecting
the design of
high-speed mux/demux and CDR. It seems this is a drawback of a 66b proposal.
Could you
please elaborate why you believe this is a non-issue?


With respect to synchronization, I think I shouldn't have used the term
"start-up", that
was an unfortunate choice (I did not imply handshaking between local and
transceivers).What I meant was synchronization procedure or hunt state . In
approaches SDL or 64b66b block code, in catastrophic situations, there is need
for a finite
period of time to aquire synchornization. Why is this specific to the Nortel
I thought in order to find the beginning of the 66b blocks, one would also
have to use
a sliding window technique combined with multiple checks before entering the
sync state.


Latency and complexity: Rick, thanks for the clarifications. I take back the
in my previous email. If it is possible to show that error multiplication is
not an issue, I also
take back my comments on CRC.


Thank you for your detailed emails and happy holidays!