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Re: [STDS-802-3-400G] IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call draft agenda

Hi Ian,

Thank you very much for your concern, but we have checked
through almost all the implementation bottlenecks, I suppose.

We can show a few sample implementations as examples, but we
think specific DSP implementation should not be a part of
our propsal or recommendations, rather, it should be left
open for individual vendors or future technologies.
It is especially true for DSP-based systemslike NPAM or DMT,
since advance in process technology and signal processing
techniques in the next several years will drastically
improve their power consumption and performances.
>If you use Nyquist sampling with the ADC running at (e.g. 1.1 >sample/symbol) and then digitally upsample to 2 samples/symbol for >clock recovery, you need a high-order FIR filter with steep cutoff >(like the one used for TX pulse shaping) to reject the image; if this >is similar complexity (41 taps?) to the TX filter, this will consume a >lot of gates and power (more than on TX because of NxN bit 
> multiply not 2xN bit) -- have you estimated this?

Yes. One of the good aspects of small roll-off factor NPAM
is its wide frequency separation between signal and its image
when interporation is done. We checked that 19-tap LPF is
enough to separate them and assume its 7-input by 4-output
polyphase FIR filter implementation, which requires far
less gate count than the 41-tap FIR filter in N x 2N
configuration.

As to the location of the Rx-side FFE, one of the possible
solution is to place it before the resampling circuit as you
said, since we think the convergence and control issues can
be overcome anyway. But if you want, you can sepearte it
into two filters; the longer semi-fixed one for the
pre-resampling FFE, and the shorter adaptive one for the
post-resampling FFE. Of cource, there may be some other
solutions.

Best regards,
Nobu

Nobuhiko Kikuchi,
Central Research Lab, Hitachi Ltd.
Yoshida-machi 292,
Totsuka, Kanagawa, 244-0817
TEL:    +81-50-3135-3104/3486
E-mail: nobuhiko.kikuchi.ca@xxxxxxxxxxx


(2014/10/07 18:51), Dedic, Ian wrote:

Dear Kikuchi-san

If you use Nyquist sampling with the ADC running at (e.g. 1.1 sample/symbol) and then digitally upsample to 2 samples/symbol for clock recovery, you need a high-order FIR filter with steep cutoff (like the one used for TX pulse shaping) to reject the image; if this is similar complexity (41 taps?) to the TX filter, this will consume a lot of gates and power (more than on TX because of NxN bit multiply not 2xN bit) -- have you estimated this?

Do you then propose the FFE needed for data recovery is before or after this interpolation filter? If before you may have problems with convergence and control, if after the power dissipation will be increased by 2x compared to 1 sample per symbol.

My concern is that you are proposing a modulation system without estimates of the overall gate count and power consumption needed to realize it, especially the blocks which consume most power like the Nyquist and FFE filters, and without addressing one of the fundamental problems of Nyquist pulse shaping with PAM4 which is the very narrow horizontal eye opening and susceptibility to jitter.

(the noisy phase error estimate problem also applies to PAM4 with 1 sample per symbol and seems to be similarly ignored)

I'm not suggesting you should consider the implementation of DMT, just the implementation of your proposed system :-)

Best regards

Ian

-----Original Message-----
From: Nobuhiko Kikuchi [mailto:nobuhiko.kikuchi.ca@xxxxxxxxxxx]
Sent: 07 October 2014 09:36
To: Dedic, Ian; IEEE_listserver
Subject: Re: [STDS-802-3-400G] IEEE P802.3bs 400 Gb/s Ethernet SMF Ad Hoc conference call draft agenda

Dear Ian,

Sorry for being late to reply.

My intention of "the small ADC oversampling (Ex. 1.1 Sa/symbol)"
is that it can be safely upsampled to 2 Sa/symbol later in DSP in the case of Nyquist PAM, if needed for the clock extraction, since the Nyquist PAM signal does not cause aliasing problem even with the small ADC oversampling.I don't think it does not contradict your story.

And I don't think I should consider the implemtentation of DMT or other systems ...

Best regards,

Nobu

Nobuhiko Kikuchi,
Central Research Lab, Hitachi Ltd.
Yoshida-machi 292,
Totsuka, Kanagawa, 244-0817
TEL:    +81-50-3135-3104/3486
E-mail: nobuhiko.kikuchi.ca@xxxxxxxxxxx
   ---------------------------------------------------

(2014/10/02 23:05), Dedic, Ian wrote:

Dear Kikuchi-san

As far as I know, a small amount of oversampling still doesn't change the fact that the resulting phase detection process in the PAM4 CDR is noisy (low gain) and has a lot of data-dependent noise, compared to 2 samples per baud where one sample is always on the steep slope of the data transition (but PAM4 still has more noise in the estimate than NRZ).

This means a lot of averaging is needed to extract an accurate phase error estimate, which means low loop bandwidth, which means high sensitivity to REFCLK and VCO noise. The problem is not the algorithm but the performance in real life when considering phase noise requirements on REFCLK and VCO. It wasn't a problem for 10G but at 100G the phase noise and jitter requirements are 10x (20dB) more stringent, this can then become a major issue which I fear is not being properly considered.

If you have some results showing that this is not the case then I suggest you present them for comparison with other approaches such as NRZ, lower-rate PAM4, and DMT.

(actually, results should be presented for all systems to show that
this is not a show-stopper for low-cost low-power realizations)

Best regards

Ian

-----Original Message-----
From: Nobuhiko Kikuchi [mailto:nobuhiko.kikuchi.ca@xxxxxxxxxxx]
Sent: 02 October 2014 05:22
To: Dedic, Ian; IEEE_listserver
Subject: Re: Re: [STDS-802-3-400G] IEEE P802.3bs 400 Gb/s Ethernet SMF
Ad Hoc conference call draft agenda

Dear Ian, Winston, and Cole

Please excuse me to express my view.

As to the timing issues of Nyquist PAM signal, Ian pointed out, there will be some countermeasures as you know, one of it is the increase of the ADC sampling ratio a bit, for example to 1.1-sample-per-symbol (Ex: 64GSa/sec for 56GBaud Nyquist PAM4 with the roll-off factor of 0.1). Such a small increase is sufficient to cover all the Nyquist spectrum and will not cause significant cost nor bandwidth issues.

I think that not only us, but other PAM4 vendors also have solutions to their implementation issues.

Best regards,

Nobu

Nobuhiko Kikuchi,
Central Research Lab, Hitachi Ltd.
Yoshida-machi 292,
Totsuka, Kanagawa, 244-0817
TEL:    +81-50-3135-3104/3486
E-mail: nobuhiko.kikuchi.ca@xxxxxxxxxxx
---------------------------------------------------