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Dear Task Force Participants, Since this was an unofficial adhoc, these notes are being provided as a good will service to the Task Force. They are not official notes, nor sanctioned by the IEEE 802.3bt Task Force. The goal of the meeting was to discuss how to attack the PSE State Diagram work to offer future comment material for 802.3bt. ------------ Notes for (unofficial PSE State Diagram Teleconference) Attendees: Gaoling Zou, Dave Dwelley, Dave Abramson, Yair Darshan, Dan Dove, George Zimmerman Preface: The total work presented was a revision to the Type 3 and Type 4 Classification State Diagram. The author's assumption was that classification would have to be run in parallel or sequentially, and therefore chose to define a sequential approach to simplify state diagram definition. If we go sequentially, we have to have each Class variable _a and _b. Specific comments Dave A: Entrances A and B cannot be changed if we support Type 1 and Type 2; If its only Type 3 and 4, they can be stripped out. Dan: I think we need to survey the TF on - The idea of pulling Type 1 and Type 2 material out of the drawing. - Running sequentially (as shown) or in parallel? (for duel sig) - Do we create dual variables mr_pd_class_detected_a and mr_pd_class_detected_b? - If sequential, do we perform PSA first, PSB second? vice versa? Yair: The way to deal with dual sig PD, you do detect/class/power independently. Dan: So we may find the proper place to perform the division at the hierarchical level, otherwise, in the case where one pair-set is powered, the other not powered, you would not be able to perform detection/classification on the pair-set that is not powered. Or you can link them at the higher level. George - thinks we should keep the logic simple. We have a maintenance situation because there are long equations with lots of ORs and this increases probability of error. Dan: Have a higher level diagram that addresses connection check and then branches down into either alt_A, alt_B, or both. The remainder of the state diagram would be treated independently, with exceptions only where a global need to drop power might exist, and those conditions would bring you all the way back up to the higher state diagram. George: A*B or A, or B One way, Type 1, 2, one way Type 3,4 with alt_A, altB, both alt_A & alt_B. Dan will go after a higher-level diagram. When do we want this? Hawaii would be good time to discuss. I have a presentation request for time on the state diagram update, so can present there. Will plan to share via reflector between now and then to get comments. Yair: Describe higher level operation for single sig and dual sig cases. How does this change the current diagram as we move down that process. Behavior under fault, For example, single signature detection can lead to class on one pair, the other or both? This needs to be described. In dual-sig case, do PSE_Alt_A and PSE_Alt_B diagrams operate Sequentially? Parallel? Asynchronous? Yair: You can do connection check before or during detection. Thanks to everyone who attended. These notes were taken while presenting, discussing, etc so may be missing pieces or incorrectly captured. If you see an error, feel free to update the record. Best Regards, |