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Hi guys, Please review final work. Regards Yair From: Picard, Jean [mailto:jean_picard@xxxxxx]
EXTERNAL EMAIL Yair See below Regards Jean From: Yair Darshan [mailto:YDarshan@xxxxxxxxxxxxx]
Did you see the mail? Thanks, Yair --------------- Hi Jean, I been told by Lennart that you were the designer of the PSE dual-sig state machine so I guess you can clarify some of my questions below. I was assigned to resolve TDL#253 from D.2 for this meeting. This was a comment from David Stover which says the following: ------------------
PSE Class SD for dual-signature PDs is inconsistent with
recent developments in single-signature Class SD. Particularly, state CLASS_4PID4 is inconsistent with the notion that pd_req_pwr and therefore pd_cls_4pid are known after 3 (not 4) class events.
Also, the "pse_allocated_pwr" paradigm is not implemented for PSE dual-signature Class SD.
TDL (Yair):
1.
Implement pse_allocated_pwr scheme from single-signature PSE Class SD into dual-signature PSE Class SD.
2.
Modify pd_cls_4pid logic such that pd_cls_4pid_* are determined out of CLASS_EV3_* states." ------------------
1.
David says that we need to sync the PSE classification SM for single signature to D2.4 page 137 and 138 PSE dual-sig SM. I understand the main differences between them (I hope..).
My question is, why to make changes just for they will use the same concept. If the current dual-signature state machine is correct, why to change it? >> JP: I think the same, unless we think it’s important to indicate the allocated power in the state diagram. If such change is to be done, it has to
be done with minimal impact on SD complexity.
2.
Regarding his 2nd point: why you locate pd_cls_4pid_pri/sec after the class event 4 and not after class event 3?
>>JP: that statement is not accurate, the 4PID block is in fact located at 2 locations, always the last block just before reaching the last Mark state (after 3 or 4 events). Why the second after 4 events? If the 4th class
is different than the 3rd, the 4PID is not set. I don’t see anything to change here, really.
Thanks
Yair
Darshan Yair Chief R&D Engineer Analog Mixed Signal Group Microsemi Corporation 1 Hanagar St., P.O. Box 7220 Cell: +972-54-4893019
E-mail: <mailto:ydarshan@xxxxxxxxxxxxx>. |
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