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Re: [802.3_4PPOE] Backfeed - presentation and baseline



Hi Lennart,

Please see below.

Yair

 

From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Friday, May 4, 2018 6:16 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] Backfeed - presentation and baseline

 

EXTERNAL EMAIL

Hi Yair, all,

 

Thanks for reviewing.

 

Several changes have been made:

 

- It is correct to say source, please see slide 7 of my presentation. The negative pair that is off, is pulled up by a resistance to +VPSE. Hence the current is coming OUT the negative pair.

Yair: I saw slide 7 and still I have this issue. PSE cant source power and cant source current if it is OFF. The unpowered negative pair cant source power. It only can be serve as a load when it is passive.

We can say "supply" rather than source, if that is preferred?

Yair: Same. How PSE can supply current when the relevant pair/pairset it is OFF?

See Joris proposal that resolves this issue.

 

In addition, this text is good to describe what happen when PSE is connected to SSPD and not for all PDs.

 

I suggest the following corrections in order to fix both issues (including Joris proposal too):

When a 4-pair capable PSE provides power in 2-pair mode, whereby two pairs are connected to the positive

VPSE, and one pair is connected to the negative VPSE, the a single-signature PD may reflect a voltage of up to VPSE back onto

the unpowered pairset. See 145.3.8.8. A PSE connected to a single-signature PD, operating in 2-pair mode, where the potential of the conductors

of the unpowered negative pair are in the range of the potentials of the conductors of the powered negative pair pairset,

shall not source cause a current higher than Irev, as defined in Table 145–20, to flow on the negative pair of the unpowered

pairset

 

- To avoid confusion, the word "backfeed" is removed from Clause 145. We're calling it reflected voltage.

This more accurately describes what is going on AND cannot possibly be confusing with the PD sourcing power on its own.

Yair: I agree that it resolves the confusion between aux sourcing power to PSE reflecting power.

 

- I've split the reflected voltage requirement into a single-signature version and a dual-signature.

Yair is right: this provides proper warning to PD designers that the situation is different.

Note: this required shuffling around the entire sentence for it to still be -somewhat- readable.

Yair: This is OK for the PD section. See above for the PSE section.

 

- The PSE requirement is updated to only hold when the unpowered pair isn't being forced outside of the supply range of the PSE.

I really struggled to make text for this. What is there is accurate I believe... but it can be said shorter / more elegant ?

Yair: Not clear to what topic this reply is referred too?

In addition: Missing text that addresses the possibility that detection will be polluted by the high backfeed voltage current per our discussions.

I have discussions with Chris and Dylan and the magnitude of the issue is now narrower however need to be verified for other behavior of ideal diode bridges.  

Meanwhile, to be on the safe side, I suggest adding the following text:

“In a multiport system, PSE port that is doing detection should not be polluted by another PSE port at any operating modes including:

a) backfeed voltage of unpowered pair. See 145.3.8.8.

b) powered pair of adjacent port."

(or equivalent text). 

 

Regarding 145.3.8.8 Backfeed Reflected voltage

I believe it should include classification too and best if it reaches 30V and not just 10.1V:

“For a single-signature PD, when any voltage in the range of 0V to 10.1V  30V is applied per any of the valid

2-pair configurations, defined in Table 145–20, including those with…..”

 

Yair

 

 

 

Kind regards,

 

Lennart

 

 

On Fri, 2018-05-04 at 13:13 +0000, Yair Darshan wrote:

Hi Lennart and all,

Please see attached my comments to your baseline attached in the file + short summary of it below:

 

In 145.2.10.3a Reflected voltage:

You have change the word draw to source which I believe it is incorrect (I saw David Stover input too.):

PSE is not sourcing in this case. It is drawing or consuming power. A device sourcing power is a device that the current is flowing out on its positive terminal to a load and return back to its negative. In our case the voltage coming to the PSE is EXTERNAL voltage (even if it is reflected or backfeed, it is still coming from the outside into the PSE PI), as a result, the PSE in this case is a load and not power source.

Please change back to “draw” or equivalent.

 

145.3.8.8 Backfeed voltage

-The changes you made are OK but it is good for SSPDs only when you restrict the backfeed requirement to 2-pair mode.

Dual-signature PDs need dedicated text in which we require that backfeed will be met for all operating modes.

It is true that DSPDs need to show valid signature on each pairset however the proposed text as is will create confusion since offset voltage (part of valid sig requirement) is not backfeed. Backfeed voltage creates a common voltage at the PSE (you remember Vc in our discussion) that will create the leakge issue that will pullot detection in a multiport system + will cause invalid detection by definition.

 

Please see proposal for modification in the file attached.

 

And last (this is per our discussion):

Missing addressing PSE sensitivity to leakage current generated by the backfeed common mode voltage and its low source resistance if backfeed is permitted in 3-pair:

Add the following text to                      :

“In a multiport system, PSE port that is doing detection should not be polluted by another PSE port at any operating modes including:

a) backfeed voltage of unpowered pair. See 45.3.8.8.

b)   powered pair of adjacent port."

(or equivalent text).

 

Yair

 

 

From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Wednesday, May 2, 2018 11:04 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] Backfeed - presentation and baseline

 

EXTERNAL EMAIL

Hi David,

 

Fair point. Made a couple changes:

 

- Used a named parameter rather than just specify 1.3mA in the text

- The current is actually coming out of the negative pins toward the PD, ergo changed the text to say 'source' rather than draw

- The PD would need to push that negative pair lower than its own negative supply for the current to increase... which would constitute 'sourcing power' and is no longer reflecting a voltage, but imposing one.

 

Kind regards,

 

Lennart

 

 

On Wed, 2018-05-02 at 19:31 +0000, Stover, David wrote:

Hey Lennart,

 

As always, thanks for your hard work on this. Seems like we’re converging on a solution. I’m still reviewing, but wanted to point out a concern I have regarding the ‘reflected voltage’ requirement:

 

“A PSE, operating in 2-pair mode shall not draw a current higher than 1.3 mA on the negative pair of the unpowered pairset.”

 

Taken in isolation, I believe this requirement is missing a critical qualification: applied voltage. Surely we do not want to enforce this requirement e.g. for applied voltage greater than PSE output voltage.

 

My proposed change:

 

“A PSE operating in 2-pair mode shall not sink current greater than 1.3mA on the negative pair of the unpowered pairset for any voltage applied in the range of 0 V to VPSE-OC, where VPSE-OC is the open circuit voltage of the powered pairset.”

 

Notice a new term VPSE-OC, to address a concern that VPSE specifies a measurement point but does not qualify who is applying this voltage. This solution attempts to clarify that the maximum applied voltage during this test should be no greater than the PSE output voltage.

 

-David

 

 


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Attachment: yseboodt_01_0518_backfeed_baseline V201 with Yair response.pdf
Description: yseboodt_01_0518_backfeed_baseline V201 with Yair response.pdf