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Re: [802.3_4PPOE] Reflected voltage - baseline v240 (UPDATE - now v250)



Hi Yair and all,

Please see updated version based on this feedback.

Wrt to the issues below:
1. Fixed, it should point to Table 145-16 in stead.
2. It is actually sourcing in this case, with a very weak current source of 1.3 / 0.5mA.

The word draw simply does not describe what is happening. I do agree that none of this is obvious or easy to understand in any way,
any reader would need complete understanding of PSE and PD implementation details to understand what current is.
We will devote several pages to this in the updated EA whitepaper.
I _am_ willing to change source into something else, to increase clarity, but it must be CORRECT.
I haven't heard any suggestion yet that increases clarity and is correct.
Irev == sourced current between two negative pairs (see slide 13)

3. OK agree, I also dislike this construction. I've made a fresh attempt at defining wat Irev is, and then create a simple shall around it.

4. That note is on the previous page from the Table, no need to move, as it pertains to the requirement directly above it.

5. I'm not touching the 10V / 21V thing until I hear consensus... otherwise we get oscillating baseline.

To those advocating for 21V ==> please show technical issues with the current proposal.

Kind regards,

Lennart


On Sat, 2018-05-19 at 01:08 +0000, Yair Darshan wrote:

Hi Lennart,

Please see my inputs in the attached file or below.

Main issues:

 

145.2.10.3a Reflected voltage

When a 4-pair capable PSE provides power in 2-pair mode, whereby two pairs are connected to the positive

VPSE, and one pair is connected to the negative VPSE, a single-signature PD may reflect a voltage of up to

VPSE back onto the unpowered pairset. See 145.3.8.8. The PSE shall not source a current higher than Irev, as

defined in Table 145–20, on the negative pair of a pairset when the voltage of that pairset is equal to or lower

than the voltage of the other pairset.

 

Issues:

1. Irev is not defined in Table 145-20. – Suggest deleting link to Table 145-20. I don’t see how it help and I only see it add confusion.

2. The PSE alternative that is not powered, can't source current. It is now passive element and serves as a load so it draws current.

3. This text allows to draw >Irev if the voltage is higher than the other pairset. Delete this part.

 

Propose to change the whole sentence to: The unpowered PSE alternative shall not draw a current higher than Irev, on the negative pair of the unpowered pairset.”

 

145.3.2 PD PI

. . .

A PD shall meet the requirements of detection (145.3.4), PD signature configuration (145.3.5), and PD classification

(145.3.6) in any valid 2-pair configuration, as defined in Table 145-20.

NOTE—this includes configurations with two pairs connected to the positive VPD and on pair connected to the negative

VPD.

 

I suggest that this note will be a text that explains what is 3-pair config and will be move to below Table 145-20 where it addressed.

 

And last:

In 145.3.5 PD signature configurations

to change from 10.1V to 21V. Need more discussions to confirm/keep this.

 

Yair

From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Thursday, May 17, 2018 10:10 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: [802.3_4PPOE] Reflected voltage - baseline v240

 

EXTERNAL EMAIL

Hi folks,

 

I've incorporated Heaths changes to PD signature and added the PD requirements for 3-pair.

 

Please check carefully - I really want to avoid making changes as this is presented next week.

We have a habit of doing that, and it frequently leads to mistakes.

 

Kind regards,

 

Lennart


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Attachment: yseboodt_01_0518_backfeed_baseline.pdf
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