04Aug04 Meeting Minutes: 802.3ap Channel Model Adhoc Conference Call Attendence: Brian.Brunn@xilinx.com brian.seemann@xilinx.com Steve.Anderson@xilinx.com rmoubarak@ti.com ahealey@agere.com john.dambrosia@tycoelectronics.com richard.mellitz@intel.com David.McCallum@molex.com tomaz@force10networks.com Dima.Smolyansky@tdasystems.com cathyl@lsil.com luke.chang@intel.com jjlynch@us.ibm.com pravinp@us.ibm.com schelto.vandoorn@intel.com glen@vitesse.com Wed August 4th Agenda: Tomorrow is conference call for signaling ad-hoc, please try to at least listen in. Since last meeting: - Joel documented the scope of what still needs to be done on the masks followed by the agenda. - Brian made a presentation on group delay. Last meeting: - Voted in Dk,Df values for improved FR-4. - We got more data presented on actual boards. - SDD21 generally came out higher than the limit line…why? - Need more data on multi-aggressor NEXT/FEXT - Need to further understand the group delay data - Joel has sent out test cards to some for their measurement. - John D’Ambrosia has support from Tyco to build a set of cards. - Signaling group will expect some convergence from us by the 1st-2nd week of Sept. so we will be driving hard. VNA averaging, with the higher resolution, do we really need to wait the 15minutes for 16averages? - Comments on repeatability from what Graeme said in his reflector. - 16 avgs/300hz – 15 minutes/measurement + 1hr cal time 20 measurements + cal can take 2 days (Joel – Agilent equipment) - Any experiences with any of these settings? - Brian (Xilinx) – Similar experience when setting up for test boards. Brian’s life was threatened when he asked for 16 samples. He went for 4 averages (under duress J ). Used Agilent equipment. - Glenn (Vitesse) – did not have any issues. Used Anritsu equipment. Single ended measurements. Joel is suggesting: 1. 2-4 averages, but we must check for repeatability. 2. 1000hz IF BW with 16 averages – faster but may have more variance. May need more averaging. Can we get data/time to measure from the group using both 4 and 16 averages? - F10 and Xilinx will compare data Straw poll – Do you agree to reducing the number of averages from 16 to 4? Yes – 1111111 - 7 No - Abstain – 111111111 – 9 We will do 4 averages, people will look at the data on the reflector and we will close the issue on the reflector SMA De-Embedding for test cards - If you have an idea on this, please send it out to the group/refelctor today. I'm open on this and would like some thoughts. - I plan to send the new run of test cards out right after we finalize the de-embedding. Two cases - 40” 2 connector and 40” 3 connector model (only need 33” in this case) - SDD11 and SDD22 levels out @ -4db - No de-embedding points for the pad - Cards will be sent out again (new ones with added traces for aggressors) 1. 3 aggressors 2. include a de-embedding point to accurately de-embed the SMA connector. We could raise the line (Joel would not recommend doing this). De-embed the SMA and keep the pad in the TX/RX spec. De-embed the SMA and the pad for the channel spec. Short discussion on the above 2 lines and how it applies to packages and clarification of who ‘owns the pad’ Up until now, IEEE has not identified who owns the pad (presumably). If the channel owns the pad then we have to define exactly what the BGA ball is. Packages do not use the same balls/pad sizes. Pad/Via structure is not completely defined by the board designer. Recommendations from the chip vendor set limits on the board. Via/dogbone/pad ownership. Adam referred the discussion back to the reference diagram (TP1 and TP4) and that we should refer to it for definition and possibly make some assumptions on the via/pad/dogbone and the ac/dc coupling losses. What are the views of the chip vendors? Discussion? - John D’Ambrosia – Old cards gave crappy Return Loss values. New cards are better, but he is not sure exactly where it came from or how to account for it. All launch structures were counter bored. - Joel – current TP4 only goes up to the DC block cap. Long term smartest way is to put TP1 and TP4 on the silicon side of things. BGA pad and via has large effect and one side or the other has to account for it and it would be easier for the chip guys to measure and de-embed than the board guys. Large degree of variability would have to be designed for and margin has to be allowed for. Does everyone understand what is meant by including the via/pad/dogbone? No comments – assume that all parties understand. Straw Poll – Vote “Yes” if it is OK to include the via/dogbone/pad with the TX and RX with ~3/8” of trace for de-embedding (TP1 and TP4). If DC block is on board we would include up to the DC block cap pad in addition to the via/dogbone/pad with the RX. With test structures to be defined later both from the channel side and from chip side as an informative. Yes – 11 No – 111 Abstain – 1 Abstain – Lack of Data – 1111111 More work needs to be done (more data) Joel will work hard over the next 2 days to close on today’s issues so we can move forward and try to keep to the schedule to meet modulation (signaling) requirements. If we do not de-embed the channels we will have to reengineer the test cards and an informative doc to tell people how to do test cards. End of call. Next meeting – next Thurs. – Crosstalk. Joel will get Brian’s group delay presentation out to Adam to place on the reflector. Please read!!!