Haven’t seen the comment on using 100 ppm spec to calculate jitter, however one should not equate frequency accuracy to jitter.
It is possible to have a very accurate clock with poor phase noise and have a clock with 100 ppm frequency error with very good phase noise.
From: Vinu Arumugham [mailto:00000960f69b1502-dmarc-request@xxxxxxxx]
Sent: Friday, January 19, 2018 2:22 PM
To: STDS-802-3-50G@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_50G] 802.3cd: Jitter Question
This email originated from outside of Semtech's email system. DO NOT click links or open attachments unless you recognize the sender and know the content is safe.
Adee, Piers,
I don't think the +/-100 ppm spec. can be used to calculate peak-to-peak LF jitter.
One could use a +/-100 ppm crystal oscillator on the host, which could operate at either edge of the spec. range. The LF jitter effect should be in addition to the +/-100ppm impairment.
Thanks,
Vinu
On 01/17/2018 11:33 AM, Ali Ghiasi wrote:
Bill
Typically DC-DC convertor will have one dominant tone output like 3rd or 5th harmonic, etc. Given today efficient DC-DC convertors operates at > 1MHz
it is much easier to filter the spurs with reasonable size low-ESR capacitor, which was not the case when DC-DC convertors operated at 50 KHz!
Obviously >1 MHz DC-DC convertor can’t generate multiple of UIs into SerDes output and pass limits we already have in place!
The analysis was done analysing a single tone.
Is it possible to get a bad spur from tones from a switching power supply that could influence the behavior in the analysis?