100 Gb/s per Lane for Electrical Interfaces and PHYs call for interest


The following request for agenda time for a 100 Gb/s per Lane for Electrical Interfaces and PHYs call for interest has been received from John D’Ambrosia. It will be discussed at the IEEE 802 LMSC November 2017 Plenary meeting in Orlando, FL, USA.

If you have any questions please get in touch with either or directly.


The continual growth of bandwidth demand has driven evolution of higher Ethernet speeds, most recently with 100 Gb/s, 200 Gb/s, and 400 Gb/s Ethernet, as demonstrated by related 802.3 projects over the past 5 years. Ongoing advancement in SERDES technology to higher rates of operation will enable the opportunity to develop improved interfaces for AUIs, backplanes, and cables at these rates. This call for interest is to assess support for the formation of an 802.3 Study Group to explore the uses and development of electrical interfaces and electrical PHYs using 100 Gb/s per lane technology.


The call for interest will take place during the IEEE 802.3 Opening Plenary on the morning of Monday 6th November. A call for interest consensus building meeting has been scheduled to occur from 19:30 to 20:30 on the evening of Tuesday 7th November. The vote to determine if a Study Group will be formed will take place at the IEEE 802.3 Closing Plenary on the afternoon of Thursday 9th November.

100 Gb/s per Lane for Electrical Interfaces and PHYs CFI consensus building meeting presentation



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Last Update: 6-Nov-17


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