PROPOSED ACCEPT IN PRINCIPLE.

Add additional power classes, including control registers, and adjust loop resistances as shown in http://www.ieee802.org/3/cg/comments/Comment_i-321_Stewart_3cg_clause_104_modifications_v1.pdf , by making the following changes:  (references to “Stewart comment i-321 presentation” below are to this URL).


Modify Clause 30 to reflect new classes as follows:
Add new edit on (P41, L20):
Change text of BEHAVIOUR DEFINED AS section of 30.15.1.1.6 as shown:

“BEHAVIOUR DEFINED AS:
A read-only value that indicates the class of the detected PoDL PD as specified in Table 104–1 <UL>and Table 104-1a<UL>.
This value is only valid while a PD is being powered, that is the attribute aPoDLPSEPowerDetectionStatus is reporting the enumeration “deliveringPower”.

If a Clause 45 MDIO Interface to the PoDL PSE function is present, then this attribute may be derived from the PD Class <UL>and PD Extended Class<UL> bits specified in 45.2.9.2.8 <UL>and 45.2.9.3.1a<UL>.;”

Update the PoDL PSE Status registers to support the new classes as follows:

Modify Table 45-340 PoDL PSE Status 1 (P62) and Table 45-341 PoDL PSE Status 2 Register Bit Definitions (P63) to extend class codes as shown on slide 7 of Stewart comment i-321 presentation.

Update the PoDL Class register and Change the last sentence of the 45.2.9.2.8 (P62) from: When read as 0000 a Class 0 PD is indicated…, and when read as 1111 a Class 15 PD is indicated.”
To:
“When read as 0000 a Class 0 PD is indicated…, and when read as 1111 the Class will be as indicated by the PD Extended Class (13.2.4:3) bits.”
Add new subclause 45.2.9.3.1a PD Extended Class (13.2.4:3) to the draft, with editing instruction:
“Insert New subclause 45.2.9.3.1a PD Extended Class (13.2.4:3) after 45.2.9.3.1. Add text under 45.2.9.3.1a as below:”
“When read as 00 a Class 15 PD is indicated. Values of 01 and 1x are reserved.”


Change the edit to last 3 sentences of the first paragraph of 104.2 Link segment (P86 L28-31) from:
“The link segment dc loop resistance shall be less than 59 ohm for Classes 10 and 13. The link segment dc loop resistance shall be less than 39 ohm for classes 11 and 14. The link segment dc loop resistance shall be less than 36 ohm for classes 12 and 15.”

To “The link segment dc loop resistance shall be less than 65 ohm for classes 10 and 13. The link segment dc loop resistance shall be less than 25 ohm for classes 11 and 14. The link segment dc loop resistance shall be less than 9.5 ohm for Classes 12 and 15”

And, change the edit to Table 104-1a (P87 L1-22) deleting the last two rows (Cable mm (AWG) and Cable Length (m)) and modifying the entries in classes 10 through 15, as shown on Slide 10 of Stewart comment i-321 presentation.

Change Table 104-4 items 6 and 7 (Page 89 L22) to change class on existing values to Classes 0 to 9, and add new row for requirements on Classes 10 to 15 as shown on slide 11 of Stewart comment i-321 presentation.

Add new entries to Table 104-7 PD Power Supply limits table (Page 91 line 20), inserting new rows 4f, 4g and 5f, 5g for turn on and turn off voltages for the 2 new groups of classes respectively as shown on slide 12 of Stewart comment i-321 presentation, and add new entry for item 7 in Table 104-7 Inrush enable delay time for Classes 10 to 15 as shown on slide 13 of Stewart comment i-321 presentation.

Change Table 104-8 item 1 (Page 95 line 10) to change class on existing values of PSE Pull-up Voltage to apply to Classes 0 to 9, and add new row for requirement on Classes 10 to 15 as shown on slide 14 of Stewart comment i-321 presentation.