Re: [HSSG] 40G MAC Rate Discussion
Marcus:
Any PCS proposal for any speed will need to be evaluated in system terms
-- how does it connect to the MAC, where are the likely exposed
interfaces and consequently signals that have to be routed between
chips, what are the overheads, how does it map to the various PMD types
(e.g., bandwidth and power impacts), what are the coding latency
implications (e.g., how is data striped across lanes, what gearbox is
required), what are the lane alignment implications (also affects
latency), data integrity implications (e.g., error multiplication
delimiter robustness), IPG implications (e.g., encoding, shrinkage) etc.
Use of 8b/10b PCS should not be assumed for a four lane PHY. Yes there
is a desire to reuse capability, most often this is within a speed
generation, but is also considered between speed generations.
10GBASE-LX4 and 10GBASE-CX4 are closely related to the XGMII/XAUI, all
being 4-lane, and yes also related to 1000BASE-X. In the 10GbE case,
the relative simplicity of 8b/10b encoding (e.g., DC balanced, simple
data striping, direct mapping to the XGMII/XAUI, low latency) were big
positives and the 3.125 GBaud signaling rate was manageable.
As you imply, 12.5 GBaud is a bit more challenging. That is why serial
10GbE backplane went with 64b/66b (10GBASE-KR) and its lower baud rate
and channel bandwidth requirements. Using 64b/66b on four lanes is more
complex but many in the group believe it is practical. The logic issues
for 4X10 Gb/s and 4X25 Gb/s are basically the same, the baud rate issues
of course are simpler at 40 Gb/s than at 100 Gb/s. On the other hand,
the logic issues are a bit different for 4X10 Gb/s and 10X10 Gb/s, but
the baud rate issues would be much the same for both.
--Bob
-----Original Message-----
From: Marcus Duelk [mailto:duelk@ALCATEL-LUCENT.COM]
Sent: Friday, April 06, 2007 7:18 AM
To: STDS-802-3-HSSG@listserv.ieee.org
Subject: Re: [HSSG] 40G MAC Rate Discussion
Hi everyone,
I have a question regarding a possible PCS implementation
of 40GbE. To my knowledge the block code is chosen according
to the PMD configuration, i.e. a 4-lane PMD will most likely
use a different PCS than a 10l-lane PMD or a serial PMD.
For 40GbE we have been arguing that the prime candidate would
be 4x10G. Looking at 10GBase-LX4 I could imagine that the PCS
of choice is 8B/10B. This would, however, result in 12.5 Gb/s per
lane. Is that a reasonable assumption or are there any reasons that
4x10G could use the same PCS as 10x10G (e.g. 64b/66b) ?
thanks
marcus
--
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Marcus Duelk
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