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Hari,
Because two bits are required to express both synchronization and control/data. If you're receiving scrambled information, a single bit indicating control/data is insufficient to delimit the 64B/66B frame. In the case of 10GBASE-T, the frame sync is performed by the LDPC frame, hence only 64B/65B is used. In 10GBASE-R, a pattern is required to perform the frame synchronization. A single bit sync would take a long time to find. A set two bit value requires less time. One two bit value indicates data, the other control. And other value would indicate a false synchronization detection.
Cheers,
Brad
-----Original Message-----
From: Hari S. patel <hari.patel@einfochips.com>
To: STDS-802-3-HSSG@LISTSERV.IEEE.ORG <STDS-802-3-HSSG@LISTSERV.IEEE.ORG>
Sent: Mon Sep 17 06:28:03 2007
Subject: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query
Hi,
I have a question on Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R).
We have two bits for sync header having following meaning,
00 - Invalid block
01 - Data block
10 - Control block
11 - Invalid block
I get confused,why we have taken two bits, even if we can indicate data/control block using one bit only.
Can I know the reason,why is it so?
Regards,
Hari S. Patel