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Hi
Mike and Math, Please
find attached the following files: Draft
D2.0 comments in HTML format. As
per Mike's request, a table which sorts the comments according to what I
believe should be resolved today at the meeting and what we can postpone to May
2008 Interim. Supporting
files, to help with resolving State Diagram related comments that were sent in
the past and were not resolved yet. Yair
Analog Mixed Signal Group Microsemi Corporation
Cell: +972-54-4893019 E-mail: <mailto:ydarshan@microsemi.com>. |
| Comment Number | Comment | SuggestedRemedy | CommentType | Clause | Subclause | Page | Line |
|---|---|---|---|---|---|---|---|
| 31 | Draft 2.0: We had allowed the PSE to turn power off if Vport is out of operating range per 33.2.9.1. Therefore the state diagram in figures 33-9 should reflect it as well. The way to do it is to create new variable which will be optional. When the conditions of this variable are met, the PSE will remove power at any t<TLIM_MIN. |
Remedy steps: 1) Add new variable option_vport_lim to 33.2.4.4. It will be an optional variable: "option_vport_lim This variable is indicating If PSE port voltage is out of operating range during normal operating mode. Values: False: Vport is within the Vport normal operating range as defined by table 33-9. True: Vport is above or below normal Vport operating range as defined by table 33-9." 2) Change state diagram (figure 33-9 per the attached drawing by changing the inputs to ERROR_DELAY_SHORT state coming from POWER_ON state, from: tlim_timer_done to: Tlim_timer_done + !tlim_timer_done*option_vport_lim*power_applied ) Effect on legacy equipment: None since the variable is optional. |
TR | 33 | 2.4.4 | 35 | 6 |
| 52 | Draft 2.0: According to the: 1. Classification base line concept and 2. Associated motions and 3. Current text in 802.3 that define that the physical layer classification information is the maximum power that the PD will ever need. the text should explicitly note that a PD that asks more power than advertised in L1 hardware classification is specifically not compliant. The rational for this was to prevent interoperability issues such as when a PD that advertized through its Layer 1 classification that it needs e.g. 12.95W and through L2 requires more power then 12.95W. In this scenario when it is connected to PSE that equiped with L2 the PD will fully work and when connected to a PSE that doesnt equipped with L2 it may or will not work. As a result we mandate PD type 2 to support both L1 and L2 classification and specify that hardware classification results are max. Power values. |
1) Add the following text right after line 29 (or other location per editor decision): "PD that asks more power (by using Data Link Layer classification than) than advertised in he physical layer classification is not compliant to this standard". Other equivalent wording is welcomed. 2) In addition add to 33.7.6.2 page 107 ,line 22 the following text. "The "NEW_VALUE" shall not be higher then specified in mr_pd_class_detected variable. |
TR | 33 | 3.5 | 72 | 6 |
| 55 | Draft 2.0 The standard should not preclude implementations that are using both alternative A and B due to the following reasons: a) It is out of scope of the standard to limit implementations. b) There are no interoperability issues if PD gets power from two 2 pairs power source. It is the load responsibility (PD) to meet the 2P specification for each 2P. Implementation methods are out of scope of the standard. c) It is economically feasible as shown in numerous presentations d) It is technically feasible as shown by the same presentations. e) There are products in the market that already is using the 2 x 2P implementation e.g. High power Midspan that is using 2 x 2P and applications that are using 2P power coming from the Switch and additional power delivered from Midspan. f) There is huge market for higher power then 30W over 2P. g) There is no additional cost issue. The $/watt cost is even lower then in 2P system as shown in previous meeting presentations. h) For outdoor applications, temperature rise issues of the cables when using 60degC cabling system grade can be solved if the same power is delivered over 2 x 2P which is an easy solution for outdoor applications. i) Users will do it any way to utilize the full capability of the existing infrastructure. J) In previous meeting switch and PHY vendors wanted the ability to use the same cable which consists of 4 pairs to support two PDs that each one of them is connected to a 2P system. The current text precludes using this feature. |
Change from: "A PSE shall implement Alternative A or Alternative B, or both, provided the PSE meets the constraints of 33.2.3. Implementers are free to implement either alternative or both. While a PSE may be capable of both Alternative A and Alternative B, PSEs shall not operate both Alternative A and Alternative B on the same link segment simultaneously." To: "A PSE shall implement Alternative A or Alternative B, or both, provided the PSE meets the constraints of 33.2.3. Implementers are free to implement either alternative or both." In addition in 33.3.1 page 33 line 42 delete "note allowed by" and replace with "out of scope of" |
TR | 33 | 2.3 | 33 | 50 |
| 64 | Draft 2.0: In many ocasions the normative text send the reader to see figures 33C.6 and/or 33C.4 which contains valuble data. These drawings should be at the normative text as it was in early drafts of 802.3af and were moved to the informative section due to editing considerations. |
Move figures 33C.4 and 33C.6 (after updating them per last changes made by draft 2.0) to the normative section at the location where they are mentioned for the first time. | T | 33 | 2.9.7 | 56 | 48 |
| 80 | Draft 2.0: The note in line 42 precludes the following applications: 1. Using two pairs to power a 10/100BT PD and using the other 2P in the same cable to power a 2nd 10/100BT PD. 2. Using a Type 2 PD that requires a total of 20W on a 2P however it was designe to take a total of 20W from both pairs. In this case this PD can work on 2P on 2x2P with the same behaviour. In addition let's assume that in this case both pairs are comming from the same box and the same power supply. This is a classical case in which by using all pairs we effectively reduce the channel power loss and allows interoperable and relaible operation. The standard should not preclude implementations that are using standard compliant 2P system. Theoretically a PD can get N x 2P power sources while each of the 2P system is well defined by the standard and the standard should not preclude it since it is implementation issue and it is not a source of interoperability issues. |
Change from: "NOTE-PDs that implement only Mode A or Mode B are specifically not allowed by this standard. PDs that simultaneously require power from both Mode A and Mode B are specifically not allowed by this standard." to: "NOTE-PDs that implement only Mode A or Mode B are specifically not allowed by this standard. PDs that simultaneously recieve power from both Mode A and Mode B is out of scope of the standard" Other equivalent wording is possible. |
TR | 33 | 3.1 | 64 | 41 |
| 107 | Draft 2.0: The text that was deleted is correct and helpful. |
Restore the deleted text. | T | 33 | 2.4 | 34 | 3 |
| 108 | Draft 2: 1. Figur 33-11 specifying the behavior of startup mode in addition to overload, short and MPS. 2. The behavior of short and startup are different in many aspects while it was similar in terms of ILIM and TLIM for type 1 legacy PSE. Now we have to separate the behavioral state diagram to reflect current changes in type 1 and type 2 PSE. We have to specify Tinrush, Iinrush for startup and ILIM/TLIM for short circuit. I believe that this differentiation will help to make clearer standards. |
Steps: 1. Replace figure 33-11 with the attached modification. Changes are: Startup and short circuit behavior has separate drawing and the same behavior of the old drawing. 1.1 Add to 33.2.4.5: "tinrush_timer A timer used to monitor the duration of the inrush condition, See Tinrush in Table 33-9." 2. Update table 33-9 accordingly (was already updated in draft 2.0..) Add item 7 to table 33-9: Tinrush min=50msec, Tinrush_max=75msec (as was before with TLIM). Add to its "additional information" column "see 33.2.9.6" (DONE IN DRAFT 2.0) |
T | 33 | 2.4.7 | 44 | 15 |
| 110 | Draft 2.0: Add clarification that Data Link Layer takes precedence over physical layer classification only when system requires using lower power than advertised by the physical layer classification. |
Replace "NOTE-Data Link Layer classification takes precedence over Physical Layer classification." With: "NOTE-Data Link Layer classification takes precedence over Physical Layer classification only when system requires to use lower power than advertised by the physical layer classification." |
TR | 33 | 2.8.3 | 50 | 34 |
| 119 | The standard allow using for each pair up to Icable. This Note prevents using all 4 pairs in a way that the total current will be Icable. The end result would be less power on the cables, less power consumption on PSE. If Icable meet the spec. of 2P then I<Icable certaily meets the same specification so preventing feeding the current all over the 4 pairs doesnt make sense. This is implementation and we are not authrized to preclude implementations that meet the numbers and state machines of this standard. |
Delete: "PDs that simultaneously require power from both Mode A and Mode B are specifically not allowed by this standard." |
TR | 33 | 3.1 | 64 | 42 |
| 140 | Add editor comment that adress the fact that this text may be subjected to changes due to the work of the 4P ad hoc | Editor note "the text that adress simultaounus operation of ALT A and ALT B may be changed as a result of the 4P ad hoc". |
E | 33 | 2.3 | 33 | 51-52 |
| 142 | The function det_pd_type returns two variables i_lim_type and i_lim_timer. Type 2 PSE can adopt type 1 variables. It is not clear according to the current text that we can do it. |
Ad text that define that "default" is the case when if after detection of PD this variable was m=not changed by the system. The system may change these two variables to Type_2 regardles of the actual readings from the PD. Rational: PSE Type 2 can use ILIM/TLIM of figure 33-14 even if PD is type 1. |
TR | 33 | 2.4.6 | 38 | 6 |
| 143 | PD may request from PSE lower power through L2 than was adverised by its hardware classification i.e. if PD is Type 1 PD with class 3, after powerup it can request less power by using L2 but it can't ask more then class 3 and convert to Type 2. If PD is type 2 which must be class 4, it can request lower power after powerup by using L2 and he cant ask for more through L2. These requirement ensures interoperbility between PDs and PSE with or without L2. This was our baseline and the results of all our discussions. In many locations in Draft 2 the editing work generate the impression that all the above may be violated by bad interpretation of the current text. Due to the fact that the state diagram determines the behaviour and not the text we need to fix the state diagram accordingly and align the text to it. |
1. Figure 33-9: add input to the "POWER_DENIDE" state which is true when the requested power from the PD through L2 is higher then mr_pd_class power equivavlent. 2. Add to 33.7 page 102 after line 10 the following text: "Type 1 PD that request more then 12.95W through data link layer classification is specifically not compliant to this standard" 3. Use the same conceptual restrictins (of step 1) in 33.7 figures 33-28 and 33-27. |
TR | 33 | 2.4.7 | 42 | 38 |
| 144 | Interoggation is not defined in the standard however detecion does. | Replace Interoggation with detection | E | 33 | 2.8 | 47 | 25 |
| 145 | We didnt agree to delete this text... Policing was optional and the text adress it was deleted. |
Restore the text: "A PSE may remove power to a PD that violates the maximum power required for its adversed class" |
TR | 33 | 2.8 | 48 | 35 |
| 146 | It is impossible to measure turn on time reliably when the voltage slope is changes dramatically from Vport=0V to ~30V while Cpd is 0.05uF and when Vport>~30V it is 5uF minimum. The turn on ramp rate was defined to limit EMI during powerup state. During power on we allow high peak current for short duration of < 10us as high as 50A. In thsi case we can never meet the requirements at 0.05uF because it will be t=CV/I=0.05uF*57V/50A = 57NS which is not practical. Our options are: 1. To delete this requirement. Rational: I is limited. Wwhen PD is connected, Cport has minimum value so V/s is limited by other parts of the specifications hence this test is redundant. 2. To specify the mesurements when UVLO is on so Vport/time=5uF/ILIM=which is the ramp during startup. 3. To measure V/s after 1msec delay. |
Replace TBD with 0.4A/5uF=0.08V/usec (change units to V/usec). In the additional information column change to 5uF. Add the text: "mesurements to be taken after 1msec." |
T | 33 | 2.9 | 54 | 23 |
| 147 | Item 21: Change Iunb to the ratio Iunb/Icable_max and replace the 10.5mA with 3%. Repete this for Type 2. Rational: Numbers are not dependent on Icable. The unbalance current is function of the unbalanced resistance between the wires. |
Item 21: Change Iunb to the ratio Iunb/Icable_max and replace the 10.5mA with 3%. Repete this for Type 2. | TR | 33 | 2.9 | 54 | 44 |
| 148 | We differentiated between TLIM and Tinrush. TLIM is for short circuit conditions and Tinrush is for startup. We did it all over the specification. |
Replace TLIM with Tinrush. | TR | 33 | 2.9.6 | 56 | 34 |
| 149 | The PSE is sourcing power not the PI. | Change PI to PSE | E | 33 | 2.9.9 | 57 | 46 |
| 150 | Figure 33-14 defines also TLIM in addition to Tovld | Change Tovld min to Tovld min/TLIM min Change Tovld max to Tovld max/TLIM max Add text to 33.2.9.9: PSE may remove power at any time between the PD upper bound template and the PSE upper bound template region. |
TR | 33 | figure 33-14 | 58 | 29 |
| 151 | The text is confusing. | Change from: "Pclass is the class power defined in 33.2.8 (see Table 33-6) or the results of Data Link Layer classification as defined in 33.7." to; "Pclass is the minimum value between the class power defined in Table 33-6 and the results of Data Link Layer classification as defined in 33.7." |
TR | 33 | 2.9.12 | 59 | 22 |
| 152 | The 3% unbalanced current was not based on simulation. It was based on 3% specification of the channel. The simulated unbalanced current was much higher then 3% and we preffered to ignor its value and leave it to the implementer to decide how to handle it. The informative section supplied the required information for that matter. |
Change to: "For Type 1 system, the values are based on channel unbalanced requirement of 3%. For Type 2 system the calculated unbalanced current is as specified in Table 33-9" | TR | 33 | 2.9.13 | 59 | 31 |
| 155 | Add editor comment that adress the fact that this text may be subjected to changes due to the work of the 4P ad hoc | Editor note "the text that adress simultaounus operation of ALT A and ALT B may be changed as a result of the 4P ad hoc". |
T | 33 | 3.1 | 64 | 44 |
| 156 | The PD state diagram is supplying a "Test Mode" like we did in the PSE state diagram. Test mode allows by passing all PD functions the prevent it from powering. In this way we can test PDs in the field if when connected to PSE something is not working and we want to isolate the problems. We can add a cautionary note as we did in 33.6.1.1.4 for the PD as well. |
add "PD TEST MODE" and "PD TEST ERROR" states to the PD state diagram. See attached drawing for reference. |
TR | 33 | 3.3.5 | 68 | 15 |
| 157 | An ERROR state is missing in the PD state diagram | Add ERROR state to the PD state diagram | T | 33 | 3.3.5 | 68 | 15 |
| 158 | Typo. Should be PD and not IPD | Delete I | E | 33 | 3.5.2 | 73 | 30 |
| 159 | Item 6: may be 25msec minimum. The max. should not be defined due to the fact that it is implementation issue. |
Change TBD to 25msec | T | 33 | 3.7 | 76 | 20 |
| 160 | Peak power for type 2 should be 0.4/0.35*Pport_max | Fix as proposed above. | TR | 33 | 3.7 | 76 | 30 |
| 161 | we change peak current to peak power | Change peak current to peak power | E | 33 | 3.7.4 | 78 | 3 |
| 162 | Figure 33G.1. is in the informative section and yet the text discuss about compliance model. | Option 1: Move figure 33G.1. to the normative section. Option 2: Delete "compliance models" and replace with "test models" |
T | 33 | 3.7.5 | 79 | 26 |
| 163 | The word "informative" is redundant. The whole 33D etc. is informative. |
Remove "informative" and scan the text for multiple locations | E | 33 | 3.7.9 | 80 | 15 |
| 164 | The title "input current" is no longer match the text. |
Replace "Input Current" with "PD Maintain Power Signature" | T | 33 | 3.8.1 | 80 | 48 |
| 165 | Item 3, the 1000BT Midspan can be also divided to items 1 and 2. | Option 1: Split item 3 to: 3) 1000BT Connector or telecom outlet Midspan PSE 4) 1000BT work area or equipment cable Midspan PSE Option 2: Delete lines 15-19 due to the fact that it is already explained in 33.4.8 page 91 lines 41-54 and 33.4.8.1 |
TR | 33 | 4.8.1 | 92 | 19 |
| 166 | In order send the draft to WG we need to complete the details here. Some of the details |
Ad hoc need to finish the work on this items at least to close TBDs. We can furnish details or numbers later |
E | 33 | 4.8.2 | 93 | 25 |
| 167 | Type 1 that requires more power then 12.95 by using Data Link Layer Classification is specifically not compliant to the standard. It can be understood from the text that we can do it. |
Add the following text after line 9: "Type 1 that requires more power then 12.95W by using Data Link Layer Classification is specifically not compliant to the standard." |
TR | 33 | 7 | 102 | 10 |
| 168 | The state diagram as it is in figure 33-27 and 33-28 allows the case of a Type 1 PD that requires more power then 12.95 by using Data Link Layer Classification. This case is not allowed (due to unteroperability issues) and according to the state diagram it is. | Add to the state diagram a state the if the PD is classified as classes 0,1,2 and 3 it can reclassify itself to lower class power then advertized by the hardware classification but not to higher class power. | TR | 33 | 7.6.5 | 110 | 27 |
| 169 |
Sorting My comments - Yair.pdf
Opt_Vport_lim Figure 33-6 rev 003.pdf