Re: [802.3_400G] 802.3 400Gb/s Ethernet Study Group Logic ad hoc
Hi Chris & Mark,
Without divulging the content of particular member contributions outside of ITU-T, I think it is safe to say that Q11 is not considering so much a classical evolution of the OTN to an OTU5, but is looking at a modular approach to constructing the OTN frame which would support the definition of not only a 400G OTN frame format, but other higher rates in the future. The module size is almost surely 100G, but like SDH, not every multiple of the module size would be a standardized rate.
If 400G were to adopt a PCS/PMA that would combine logical lanes into physical lanes using a method like bit multiplexing that didn't require the module to understand the meaning of any of the bits, then ITU-T could use an approach where each 100G module looked a lot like an OTU4 frame, the aggregate was formed by interleaving of these modular frames, and a method similar to current OTL striping could be used to divide the OTN frame into logical lanes.
If the pluggable modules would care about the bit values, would need some marker in the bit stream to find RS codeword alignment, would interleave on 10-bit symbol boundaries, etc., this would push OTN toward a different kind of framing that allowed for including the marker that the modules need to determine interleaving, and if the principle of interleaving is such that the modules are doing something assuming a 10-bit FEC codeword so as not to hamper the burst error tolerance of the code, etc., that would probably also say it would be more optimal for OTN to base its IrDI FEC on a 10-bit codeword size.
While this is something that can certainly be done, one concern I have is about the longevity of the architecture. We picked an architecture in 802.3ba that we thought had some legs to live into future generations, and we certainly did a few workshop presentations describing how that architecture might extend to 400G or 1T. Now we are discussing doing something different, and a major driver for this is the idea that Ethernet would have a native FEC.
The native FEC may well be an aspect that justifies an architectural change from what we had in 802.3ba. But if we are going to make this kind of a change at 400G, do we think this architecture now has legs to extend to higher rates in the future?
ITU-T is looking at approaches that would allow the extension from 400G to 1.6T or 1T or whatever comes next to be done in a "cookie cutter" fashion by changing the numbers of interleaved modular frames. If this modular format needs to be adjusted to allow going through 400G PMAs that are finding 10-bit alignment by looking for AM0 and then 10-bit interleaving, do we believe that this architecture and Ethernet framing is something that has the legs that we will do the same for 1.6T Ethernet, or is this a "one generation" architecture that we will see only at 400G and then 1.6T will do something else?
If a decision in P802.3bs might push ITU-T to make a change to the OTN frame format, it would be good if we are confident that this only happens once and that we don't need to tork around the OTN frame format again with every new rate.
So maybe a good exercise to go through is to draw up what it looks like to reuse this PCS architecture for 1T or 1.6T and see if it still seems to make good sense. If not, maybe we can find something a bit more future-proof.
Regards,
Steve
-----Original Message-----
From: Chris Cole [mailto:chris.cole@xxxxxxxxxxx]
Sent: Monday, December 02, 2013 11:21 AM
To: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_400G] 802.3 400Gb/s Ethernet Study Group Logic ad hoc
Hi Mark,
Another consideration when exploring PCS architectures is OTN
compatibility.
As pointed in multiple contributions, two primary initial applications
are in the central office for server to server and server to transport
links. The optics used for these applications are multi-rate, if we use
40G and 100G as a guide, for example supporting both 100GbE and OTU-4
for 100G links. For 400G we should expect that optics will support
400GbE and OTU-5 rates. This leads to the desire to maximize the
commonality between optical specifications and functionality between
400GbE and OTU-5. If 400GbE PCS requires block muxing, then the OTU-5
functionality maybe different if OTU-5 retains bit muxing. Further, the
performance maybe different as the FEC is applied differently to the bit
streams. This could increase verification and test time.
Having the PCS definition result in different optics functionality
between 400GbE and OTU-5 modes would not make it OTN incompatible, but
would complicate OTN support.
Chris
-----Original Message-----
From: Mark Gustlin [mailto:mark.gustlin@xxxxxxxxxx]
Sent: Friday, November 15, 2013 12:33 PM
To: Chris Cole
Cc: STDS-802-3-400G@xxxxxxxxxxxxxxxxx
Subject: RE: [802.3_400G] 802.3 400Gb/s Ethernet Study Group Logic ad
hoc
Chris,
> One of the topics discussed during this week's 400G SG meeting was
> trade- off between PCS and PMA complexity.
>
> We faced the same trade-off during 100G SG, and it may be beneficial
> to go back and look at some of the reasoning that went into the
> definition of 100G PCS.
>
> In particular, Mark Nowell and Gary Nicholl presented several lessons
> learned from 10G, one of which is to keep the PMD simple.
>
> http://www.ieee802.org/3/hssg/public/sep06/nowell_01_0906.pdf#page=1
> 9
In the slides you point to, Gary and Mark talk about the complexities in
putting a complete PCS sublayer into the module.
What was presented in my slides this week was the possibility of doing
block muxing in the module; only when you have to change widths and if
you want to preserve the error detection capability of the RS-FEC in the
face of burst errors (if the medium you will run across has a high burst
error probability).
Block muxing vs. a complete PCS is a much different level of complexity
for the PMD; but of course bit level muxing is simpler still and would
be the goal as long as it meets the needs of the PMDs.
>
> 100G also offers a similar lesson, where even a simple 10:4 bit
> gearbox created many complications in the physical layer. The current
> generation of 4x25G I/O modules is significantly simpler to develop
and test.
Any time you are not changing lane widths or encoding you will expect a
very simple module, with just retimers.
>
> In 400G, we should look for ways to keep PMDs simple and avoid
> requiring awareness of higher layers in the physical layer.
I completely agree that we want PMDs to be as simple as feasible.
Once we make progress on choosing technology for our new PMD objectives
then we can explore error models of the PMDs, and explore PCS
architectures which are appropriate for those PMDs.
Thanks, Mark