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During the discussion of the baseline proposals at Architecture and Logic Ad Hoc meeting on June 30th, I asked a question on BER and FLR analysis for the two 800GE PCS/PMA baseline proposals, offline discussion is suggested. I am also aware of some discussions on clock content and DC wander.
For the upcoming meeting next week, I plan to present the option 2 (Speed-up CL119) 800GE PCS/PMA baseline proposal with further data and concerns on the FLR, DC wander and clock content issues based on input from last meeting.
Please receive the attached presentation for review.
Any comments, questions, or suggestions are welcome.
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800GbE PCS and PMA Baseline Proposals for 100 Gbps per lane PHYs 20220705 s.pdf
Description: 800GbE PCS and PMA Baseline Proposals for 100 Gbps per lane PHYs 20220705 s.pdf