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Hi Wei, Thanks again for the prompt response. For me the key sentence in your response is “In SEND_TA, In the high-speed direction, the QUIET period is very short (773.3 ns), so the signal eye remains open after QUIET, and there’s no echo, therefore fast
CDR can be used to quickly adjust timing loops.” I had been making the following assumptions:
The sentence I quoted appears to imply that the high data rate receiver is tracking the clock of the high data rate transmitter. This would not be consistent with my two assumptions above. Are my assumptions that the slave tracks the master clock (and not vice versa) incorrect for the New-TDD? Ragnar From: Wei Lou <000047a3c8c56bbe-dmarc-request@xxxxxxxxxxxxxxxxx>
Hi Ragnar, I believe this thread is mainly focused on the text proposal, including block diagrams and signal definitions. So it might not be the best place to dive
into the training process and related technical details like clock stability ZjQcmQRYFpfptBannerStart
ZjQcmQRYFpfptBannerEnd Hi Ragnar,
I believe this thread is mainly focused on the text proposal, including block diagrams and signal definitions. So it might not be the best place to dive into the training process and related technical details like clock stability or jitter requirements. Those topics would be better suited for a separate presentation.
That said, let me briefly address your question.
While the TDD proposal shares some similarities with the EEE LPI operation in 802.3bp/ch, there are advantages due to the nature of the TDD approach.
After the SEND_TS (symmetric training) phase, the SLAVE is frequency-locked to the MASTER clock. This means the initial PPM offset during SEND_TA is much smaller—typically in the low single digits, not 50 ppm—because otherwise the SLAVE wouldn’t maintain loc_rcvr_status = OK during SEND_TS.
In SEND_TA, In the high-speed direction, the QUIET period is very short (773.3 ns), so the signal eye remains open after QUIET, and there’s no echo, therefore fast CDR can be used to quickly adjust timing loops. Therefore, your concern about needing 8 frames (as in 802.3ch, PAM4) to achieve symbol/frame sync before data traffic doesn’t apply here. After the initial PAM2 refresh header, the eye remains wide open through the PAM4 RS-FEC frames.
In the low-speed direction, the MASTER uses PAM2 modulation, which is more directly comparable to 802.3ch’s PAM2 refresh/quiet cycles. In 802.3ch, symbol and frame sync is maintained even with a refresh/quiet ratio of 1:95. In our TDD proposal, the refresh header to QUIET ratio is 1:42, and the total TX(burst) time to QUIET ratio is 1:16. With no echo and similar timing behavior, we believe the proposed TDD scheme can maintain sync just as effectively. The new TDD proposal QUIET time is only around 9 us, which is a fraction of the 802.3 ch at similar symbol rate.
Wei
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