Re: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query

["Trowbridge, Stephen J (Steve)" <sjtrowbridge@xxxxxxxxxxxxxxxxxx>]

Title:

Hari,

This is old stuff, but the basic reasons are to provide a guaranteed transition at least once per block (even if you give a reverse scrambler pattern as data), and to provide a method for framing (finding the start of the 66B blocks). There are certainly other ways to represent the same information in fewer bits (see, for example the 512B/513B coding proposed as an option for mapping 40 GbE into standard OPU3 in http://www.ieee802.org/3/hssg/public/sept07/trowbridge_01_0907.pdf), but these would generally require a SONET or OTN-like framing pattern to find the start of a block.

Regards,

Steve

---

From: Hari S. patel [mailto:hari.patel@einfochips.com]
Sent: Monday, September 17, 2007 7:28 AM
To: STDS-802-3-HSSG@LISTSERV.IEEE.ORG
Subject: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query

Hi,
I have a question on Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R).

We have two bits for sync header having following meaning,

00 - Invalid block
01 - Data block 
10 - Control block
11 - Invalid block

I get confused,why we have taken two bits, even if we can indicate data/control block using one bit only.
Can I know the reason,why is it so?

Regards,
Hari S. Patel