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All:
Pat's
second paragraph highlights an important item to remember. Since many in
HSSG may not have been through specification of a complete PHY, I'll risk
restating what may be obvious to HSSG participants that have been through
this before. The working group has, since its beginning, paid serious
attention to the undetected error characteristics of proposed link
technology. The base error rate of the PMD and medium are a major
factor in the mean time to false packet acceptance; and the characteristics
of the PCS running over that PMD are also important. How data is stripped
over lanes (error multiplication and CRC coverage of any error multiplication)
and other factors will have to be considerations for each PHY type. As
Pat's explanation below alludes to, delimiter robustness is important because of
its effect on the undetected error rate.
It is
still early in the process, but when it comes down to selection of baseline
proposals, I expect I'll not be the only 802.3 member asking about the
undetected error rate of proposed baseline PHYs.
--Bob From: Pat Thaler [mailto:pthaler@BROADCOM.COM] Sent: Monday, September 17, 2007 3:32 PM To: STDS-802-3-HSSG@LISTSERV.IEEE.ORG Subject: Re: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query Hari,
There are two reasons.
One is in the name "sync header." One always has a
transition between the two bits of the sync header. The rest of the 66 bit block
is scrambled so at any other position between two bits of the 66 bit
block one has a 50% chance of having a transition. This is used to obtain block
sync.
The other reason is error detection robustness. If there
was a single bit difference between a data block and a control block, one could
create a false end of packet or start of packet with two bit errors. For
example, one might have two data blocks in sequence in a packet where the block
payload was the same as the block payload in a valid end of packet followed by
idle. If bit errors in the sync header turned both those into control blocks,
then a false end of packet could be created with two bit errors and if the last
4 bytes of the false packet happened to match the CRC we would deliver a false
packet. With a 2 bit sync header, it takes a minimum of 4 bit errors to
create a false start or end of packet giving us a 4-bit Hamming
distance.
Pat From: Hari S. patel [mailto:hari.patel@einfochips.com] Sent: Monday, September 17, 2007 6:28 AM To: STDS-802-3-HSSG@LISTSERV.IEEE.ORG Subject: [HSSG] Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R), query I have a question on Clause-49 (Physical Coding Sublayer (PCS) for 64B/66B, type 10GBASE-R). We have two bits for sync header having following meaning, 00 - Invalid block 01 - Data block 10 - Control block 11 - Invalid block I get confused,why we have taken two bits, even if we can indicate data/control block using one bit only. Can I know the reason,why is it so? Regards, Hari S. Patel |