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Everyone,
"I think
this is a good point. We had much discussion regarding this. The whole idea is
that TP4 to TP5 was supposed to be owned by the chip. As a chip vendor, we
don¡¯t like this. I suggested that if TP4 to TP5 was not transparent
(+/-?), then it needs to go into the TP1 to TP4 budget. In my opinion the issues
was not adequately resolved. "
I do find TP4 to TP5 belongs to the chip in Page
80 from IEEE 802.3 AP 0.8 draft. From
the point of view of SI, placing ac capacitor in chip is
obviously better than placing it in the linecard for 10GBASE-KR
application, because if we place it in chip, the vias will be
surely smaller than those in linecard and via stub will also be
reduced greatly. I agree TP4 and TP5 owned by
the chip.
Another opinion:
I think it is necessary to add a built-in
oscilloscope in the receiver side, except BIST function. As we
know, we usually see a closed eye from an independent
oscilloscope through probing at the pin of receiver. if there is a built-in
oscilloscope , which make the analysis and parameter adjustment becomes
easier.
Any comments ?
-----Original
Message-----
From:
owner-stds-802-3-blade@LISTSERV.IEEE.ORG
[mailto:owner-stds-802-3-blade@LISTSERV.IEEE.ORG] On Behalf Of Mellitz, Richard
Sent: Monday, March 21, 2005 2:03
PM
To:
STDS-802-3-BLADE@LISTSERV.IEEE.ORG
Subject: Re: [BP] Opinion about the
Channel Model Ad Hoc
¡°Does this mean
the channel will meet all the scope at the same time ? ¡°
I think
the simple answer is YES. I think there is only one channel
spec.
¡°2) As for
the channel model, I think the channel specifications from TP1 to
TP5 is important, especially for 10G serial application. for 1G per lane and
3.125G X 4 lanes application, maybe we can ignore the
influence caused by the component from TP4 to TP5 (two line card vias and
a compactor), since before 3G Hz, the via's influence is
limited, however, for 10G serial application, especially for NRZ
coding, line card vias also play a great role for the channel
performance. According to our simulation result, for the via routing in layer
2 (line card is about 2.5mm thick), beyond 5 GHz, the insertion loss of the
via drop's sharply. We need define specifications from TP1 to
TP5, instead of the specification form TP1 to TP4.
¡±
I think
this is a good point. We had much discussion regarding this. The whole idea is
that TP4 to TP5 was supposed to be owned by the chip. As a chip vendor,
we don¡¯t like this. I suggested that if TP4 to TP5 was not transparent
(+/-?), then it needs to go into the TP1 to TP4 budget. In my opinion the
issues was not adequately resolved.
Richard
Mellitz
Intel
Corporation
Columbia,
SC
From:
owner-stds-802-3-blade@LISTSERV.IEEE.ORG
[mailto:owner-stds-802-3-blade@LISTSERV.IEEE.ORG] On Behalf Of Jia Gongxian
Sent: Thursday, March 17, 2005 8:34
PM
To:
STDS-802-3-BLADE@LISTSERV.IEEE.ORG
Subject: [BP] Opinion about the Channel
Model Ad Hoc
Hi all IEEE P802.3ap Task Force
Members,
I have been concerned for IEEEE
802.3 ap Task Force for a long time, and have read through all the
relevant materials available from the website up to now. I do hope I
have a chance to discuss with all members about the project as a
system backplane designer, to share what I think about it. Since it is
inconvenient for us to take part in the face to face meeting and
teleconference, I hope I can use the "e-mail reflector" as a platform to share
with you all.
The following is what I want to
know and what I care about most:
1) From the object
objective, the project will cover 1 G per lane, 3.125 GbpsX4
lanes and 10Gbps per lane. Does this mean the channel will
meet all the scope at the same time ?
For the legacy backplane used for
around 1 Gpbs , most of them is made of common FR4 and general
connector,such as 2mm connector without shield pin. I think it is very
hard to upgrade to serial 10 Gbps, at most up to 3.125 Gbps,
economically.
For the legacy backplane used for
around 3.125Gbps per channel, we still use common FR4, not
improved FR4, and apply common manufacturing
technology.
For the NRZ coding 10Gbps
application, if we use this kind for backplane, I think this is very hard
to realize. Thus I think for serial 10G backplane, we may using
Greenfield backplane, not legacy backplane.
According to our simulation and
measurement results, the insertion loss of channel up to 3 GHz or so, is
mainly effected by attenuation of copper loss and dielectric, impedance
discontinuity caused by trace and connector, beyond 3 GHz, the via
stub play a more and more important role, firstly, backplane via stub,
secondly, line card stub.
Given we want each
layer in PCB can be routed high speed signals,for NRZ coding 5/6 G
application, backplane via maybe need be backdirlled, for NRZ
coding 10 G application, line card via maybe backdrilled
also.
Does this project plan to using
common PCB technology to make the backplane and linecard ? or using
backdirlling and other technologies to reduce the via
stub ?
2) As for the channel model,
I think the channel specifications from TP1 to TP5 is important,
especially for 10G serial application. for 1G per lane and 3.125G X
4 lanes application, maybe we can ignore the influence caused
by the component from TP4 to TP5 (two line card vias and a compactor),
since before 3G Hz, the via's influence is
limited, however, for 10G serial application, especially for NRZ
coding, line card vias also play a great role for the channel
performance. According to our simulation result, for the via routing in layer
2 (line card is about 2.5mm thick), beyond 5 GHz, the insertion loss of the
via drop's sharply. We need define specifications from TP1 to
TP5, instead of the specification form TP1 to TP4.
3) As for the test sample, I think
we should define some specifications to guide how to design. The
test samples must actually reflect the real product design,
or else, the measurement result and
conclusion according to the result is meaningless. For
example, different types of test launches we used will greatly influence
our test result. I think the rules is, the design will reflect the practical
design, not just for test. For instance, we can use optimized SMT sma
and with a PTH (plated through hole) with 8/10 mil diameter to
reflect the BGA via in practice.
4) As for the channel
crosstalk, some member have mentioned using power sum to define the
spec, however, the project is aim at high speed digital application, all the
standards are defined as voltage in practice, such as eye height,
imput sensitivity, ect. We usually using voltage sum to calculate the
worst case of crosstalk, not power sum.
5)As for
the Serdes, It's better to integrated ac compactor into
Serdes, which will significantly improve the channels performance, for
we can reduce 2 line card vias and a compactor in linecard. Serdes for
10G serial applications must have adaptive equalization and BIST
function.
Any comments will be
welcomed.
Jia Gongxian
Huawei Technologies
Co.,Ltd.
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