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RE: [802.3af] Contradiction in Table 33-5

Hi Mike,

1.  Table 33-5 item 1 specify the output voltage at Power On state which is
normal operating conditions.
    Further more, it is specifying line and load regulation as described in which is the "additional
    information" for item 1.
    At this point it is very clear that we are discussing about normal
operation due to the fact that line and
    temperature regulations applies only at normal operating mode.

    And if this is not enough, look at item 2 that's define the range of
Vport which is item 1 at normal
    operating loads which is 0.44W to 15.4W.

    In addition, item 3 defines the ripple and noise under normal load

    And last, item 4 defines the max current values under normal conditions
so items 1,2,3,4 describes
    the normal conditions.

2.  Items 10 and 11 define short circuit condition which requires you to
limit the current.
    WE DO NOT need to say that under this conditions Vport may be lower than
    This is the physics and physics doesn't require additional definition in
the spec. It is redundant.
    If it helps you in any way, we can add a text to paragraph
saying explicitly that "Vport may be lower than 44V during
    current limit condition as specified in items 10 and 11." 

3.  The need for current limiting is also specified in paragraph 33.4.2
"Fault tolerance" page 69 line 31 at draft 4.2:
     "The PSE PI shall withstand without damage the application of short
circuits of any wire to any other wire
       within the cable for an indefinite period of time. The magnitude of
the current through such a short circuit
       shall not exceed I LIM max as defined in Table 335,item 10."

4.  I agree that figures 33c.4 and 33c.6 are in the informative section and
are not part of the standard however they reflects the text 
     in table 33-5 and the relevant sections in 33.2.8.
     Further more, the standard in paragraphs,, and send you to see those drawings 
     to make sure that the reader will understand the text as the poet meant
to say.
     If it help, we can copy drawings 33c.4 and 33c.6 to  paragraph 33.2.8.

5.  Why current limiting is required?

     Because after 4 years of discussion and testing and simulations and
many presentations from chip vendors and system vendors
     and above all to meet IEEE802.3af objectives which is to protect the
infrastructure, we specified the need for the current limit function.
     It is true that after getting to the point of 450mA or so and
shutting of the port you meet some of the above requirement however HOW you
differentiate between 
      real event of short circuit or current transients that generates false
overloads? The only way to overcome this is to filter this events by NOT 
      responding quickly to any event but to limit the current and wait TBD
ms and then to decide. The TBD ms was chosen to be 50ms to 75ms in table
33-5 item 11.

     The list of the scenarios that generates false overload was presented
and tested and was the base on which we build the spec.

     Please not that the above required behavior is not new, any power
supply meet this and the PSE port was specified in such a way to emulate 
     the behavior of standard power supply output.

6.  In addition, You are required to support Inrush current capabilities
between 400mA to 450mA for 50ms min, 75ms max to a PD with up to 180uF at
its input.
     Inrush current limiting is required by the standard. Inrush current
during startup is exactly the same condition like facing short circuit.
     In both cases you need a current limiter, that's why we specified the
same numbers for max current and time for inrush current during 
     startup and during short circuit to simplify the design because in any
case you need this hardware.

7.  Stating from your question: "Why PD current spikes, Ripple over 400mA,
PSE voltage steps require current limiting.  PDs aren't allowed to exceed
400mA at any time"
     It is true that PDs are not allowed to take more than 400mA but what if
it is faulty PD that put a short as a load? You need to limit the current.
     You ask why to limit? I can just turn OFF the port right? but when you
are going to turn off the port after 1us? BAD you are too sensitive, any
current spike will turn on your protection circuits, after few ms, possibly
yes, we specified 50ms min. 75ms max, as explained in 5.

"Ripple over 400mA": this is not the issue here, it is handled by the
overload definitions.
"PSE voltage steps require current limiting": PSE voltage steps can be
generated by the PSE or by The PD loads. They generate current spikes.
 The current spikes can be 10-15A for few us or up to 450mA for 30ms or so.
to cover all that range you have to take the worst case.


-----Original Message-----
From: Mike_S_McCormack@xxxxxxxx [mailto:Mike_S_McCormack@xxxxxxxx]
Sent: Monday, March 31, 2003 10:08 PM
To: stds-802-3-pwrviamdi@xxxxxxxx
Subject: RE: [802.3af] Contradiction in Table 33-5


I separated my response from the original text, it was getting confusing
for me.

I think we will need a comment as, even if I agree that current limiting is
the "proper" behavior, Table 33-5 item 1 requires that you maintain a
floor of 44 volts - its a hard requirement.  I would find it hard to limit
output current if I can't vary the output voltage (if the load is
constant.)  There is no exception for item 1 that allows you to drop the
output voltage to accomplish current limiting.  Granted, I want to end this
thing and print, that is why I'm hitting the reflector first, but doing
nothing is not the right answer.

I don't understand the reason why any of the following:
1.1) PD current spikes
1.2) Ripple over 400mA
1.3) PSE voltage steps
require current limiting.  PDs aren't allowed to exceed 400mA at any time
so a 451mA hard shut-off would allow margin for the leading edge of current
spikes and/or ripple on the allowed 400mA.  I don't see why every PSE needs
to be support switching over to batteries as I don't remember mandating
backup power, allowing some current limiting might be nice as a mechanism
to facilitate PSEs which contain batteries, but you're burdening every PSE
for one special application.

33c.4 is in an informative annex, it carries no weight in the evaluation of
what is compliant and what is not.

2.1) Item 11 is the timing for what to do while the output current is in
the range described in time 10.  If the current is outside the range in
item 10, item 11 is irrelevant.
2.2) Figure 33c.4 is in an informative annex and does not carry any weight
in determining what is actually required by the spec.  Further, the test
cases do not describe drawing more than 400mA , nor for that matter does
the follow on test case ever say you try to exceed 450mA, but that is also
just informative.  The drawing 33c.6 requires that you maintain at least
30V at Vport - how can you do that if it is a hard short while limiting the
current to less than 450mA?

If anything, the second behavior, of going past 450mA and shutting off, is
the only thing that really meets the specification.  I would interpret Item
10 and 11 to be the definition of a short circuit, any PSE observed power
draw in that range is defined to be in the "short circuit range".  Once the
PD exceeds the ranges in the spec, the PSE is free to do as it chooses, and
it has faithfully maintained the output voltage requirement until the PD
drew it offside and beyond the spec.  Current limiting a true short circuit
(not an excessively thirsty PD) will force the PSE to fall outside the
output voltage range and therefore violate the spec.

While current limiting the PD may be something we allow, to require the PSE
to force compliance on a PD that throws a crowbar across the line, with a
5% duty cycle of course, is a bit much for me.


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