100BASE-T -> 1000BASE-T Scaling Issues and Solutions Sailesh K. Rao Silicon Design Experts, Inc. Ph: (908)-972-0707 x11 e-mail: sailesh@sde.com IEEE 802.3 GTF, Vancouver, BC. November 11-14, 1996. 1. Main Topics - Overview of FDX 100BASE-T standards - An Obvious Scaled 1000BASE-T solution - Scaling Issues and Proposed Solutions - Code Redundancy and Usage - Putting it all Together 2. Overview of FDX 100BASE-T standards - 100BASE-Tx - 2 pairs of UTP-5 - 125MHz symbol rate - MLT-3 3-level signalling, 4B-5B encoding - SNR requirement for BER=10^-10 is 19.3dB 3. Overview of FDX 100BASE-T standards - 100BASE-T2 - 2 pairs of UTP-3 or better - 25MHz symbol rate - PAM5x5 5-level dual-duplex signalling - Uses Echo and NEXT cancellers - SNR requirement for BER=10^-10 is 24.0dB - Polarity, pair-swap, differential delay compensation 4. 100BASE-T2 Symbol Constellation 5. 100BASE-T2 PCS Transmit (Informal) 6. 100BASE-T2 PCS Transmit (Official) 7. An Obvious Scaled 1000BASE-T Solution 8. Overview of Scaled 1000BASE-T - PCS Section - Double up 100BASE-T2 PCS Section to get 8B-4P encoding - State-synchronized Cipher-Text scramblers between Pairs A,B and Pairs C,D. - Reuse of PCS and PHY Control sections from Clause 32 - PMA Section - Use 100BASE-Tx symbol rate and pulse shaping - Scale levels to -500mV, -250mV, 0V, 250mV, 500mV. - Reuse of Sections 8-11 of ANSI X3.263-1995 TP-PMD specs. 9. Scaling Issues - Receiver Analog Complexity Increase - Need 4 125MHz ADCs - Receiver DSP Complexity Increase - Equalizer Complexity remains the same as 100BASE-T2. - Echo Canceller Complexity increases by a factor of 50 over 100BASE-T2. - NEXT Canceller Complexity? 10. Reconstructed Receiver Eye Diagram - Looks good. 11. Channel Response with Worst-Case Echo 12. NEXT Canceller Complexity - Simulated under Extreme Worst-Case Conditions - Worst Case ERL Curve from DEC - Worst Case NEXT Curves from BRC - 100m UTP-5 Cabling at 60 deg. C - Receiver Parameters - 7-bit ideal 125MHz ADC - 6T Feedforward + 12T feedback filters - 150Tap Echo Canceller - SNR as a function of NEXT canceller length NONE-22dB 10taps-24dB 30taps-26dB 50taps-27dB 150taps-29dB 13. Solutions for the Complexity Issue - Decrease Symbol Rate - Echo/NEXT canceller complexity is proportional to the SQUARE of the symbol rate. - Split-Band Approach - Splitting fundamentally reduces the Echo/NEXT canceller complexity by a factor of 2. - Difficulties with Noise Immunity - Crane Test. - Decrease SNR requirement for the Scaled 1000BASE-T system with BETTER 8B-4P encoding! - The Enhanced Tx/T2 proposal. 14. Code Redundancy and Usage 15. KEY OBSERVATION - With four 5-Level symbols, we can code 5^4 = 625 distinct points. - To transmit 8 bits, we need 256 distinct points - Therefore 8B-4P encoder has more than 2-1 built-in code redundancy - This redundancy can be used to decrease SNR requirement from 24.0dB to 18.8dB, i.e., LESS THAN THAT FOR 100BASE-Tx! - Extra 5.2dB "gift" can be traded off for NEXT canceller/Echo Canceller/ADC complexity. 16. Redundant Codes - In Normal Dual-T2 Signalling - ESC Codes are not allowed during data except for SOP/EOP. - Enhanced T2 Signalling - Single ESC Codes are allowed during data. - Multiple ESC Codes are used for SOP/EOP. 17. Change to 100BASE-T2 PCS Section - Only Symbol Mapping BOX changes - Otherwise 100BASE-T2 PCS section can be completely reused. 18. Code Usage during DATA - Normal Data Codes - 4^4 = 256 points - Single ESC Data Codes - 4X4^3 = 256 points - Therefore, every transmitted byte can be protected with a parity bit using single ESC data codes 19. Parity Encoding - A Convolutional Encoder 20. Symbol Partitioning in Enhanced Tx/T2 21. Subset Partitioning in Enhanced Tx/T2 22. Subset Partitioning in Enhanced Tx/T2 - Restricting to at most one ESC per symbol reduces the number of points in each subset Di, to exactly 64 points - Used to code most significant 6-bits of GMII word. - 0.8dB increase in SNR requirement due to higher energy of single ESC data codes. - Least Significant 2bits + Parity bit is used to select one of 8 subsets. - 6dB reduction in SNR requirement - SNR required for BER=10^-10 is 18.8dB. - If parity encoding is disabled, only even subsets are used - the squared distance between valid points is still DOUBLE that for normal T2. - 3dB reduction in SNR requirement. - SNR required for BER=10^-10 is 21.8dB. 23. Taking Advantage of PARITY Encoding 24. Bit Budget for Viterbi Decoder - Compute Round Trip Delay without Viterbi Decoder - Apportion Rest of 512Byte-Times over 4 Viterbi Decoders - Max. Latency for Each Viterbi Decoder is 20Byte-Times 25. Estimated Noise Immunity - Normal T2 - With normal T2 per-pair sinusoidal noise immunity is 60mV peak-to-peak (30mV peak) - extrapolated from 100BASE-T2 numbers. - With Parity Encoding - Per-pair sinusoidal noise immunity is 120mV peak-to-peak or 60mV peak. - Without Parity Encoding - Per-pair sinusoidal noise immunity is 80mV peak-to-peak or 40mV peak. 26. Putting it All Together 27. The Enhanced Tx/T2 proposal - "Dualized" 100BASE-T2 PCS - Use redundancy to do parity encoding - 100BASE-Tx PMA - Simple reuse of existing 100BASE-T standards to achieve 1000BASE-T! 28. Other Considerations - Does not increase symbol rate to 166.67MHz and exacerbate Echo/NEXT canceller complexities by another 80%. - Without Viterbi Decoding, needs 21.8dB SNR at a symbol rate of 125MHz for a BER of 10^-10. PAM3X3 needs 20.5dB but at 166.67MHz symbol rate. - With Viterbi Decoding, needs 18.8dB SNR at a symbol rate of 125MHz for a BER of 10^-10. PAM3X3 needs 20.5dB but at 166.67MHz symbol rate. - Can work with existing cabling specifications. No need to plead for relief on ILD, e.g. - Reasonable Noise Immunity even with 1V ptp signalling.