Update on the Enhanced Tx/T2 Proposal for 1000BASE-T Sailesh K. Rao Level One Communications, Inc. Ph: (908)-972-0707 x11 e-mail: sailesh@level1.com IEEE 802.3 GTF, San Diego, CA January 27-29, 1997. 1. Main Topics - Anatomy of a 1000BASE-T Transmitter - Why NRZ Pulse Shaping? - Why 5-level Encoding? - The TABLE - Concluding Remarks 2. Anatomy of a 1000BASE-T Transmitter 3. ANY 1000BASE-T Transmitter - 125MHz 8-bit GMII Input - XMHz, Y-Level encoding - Pulse-Shaping on 4-pairs - Questions for us to Answer: - What should the symbol encoder/symbol rate be? - What should the pulse-shaping be? 4. Option A- The Enhanced Tx/T2 Proposal - X = 125MHz, same as GMII - Y = 5Levels, same as 100BASE-T2 - NRZ Pulse shaping spans ONE symbol and requires just 125MHz ADCs and DACs. 5. Option B- CAP/QAM-25 - X = 125MHz, same as GMII - Y = 5Levels, same as 100BASE-T2 - Uses Two Hilbert-pair Pulse shaping transmit filters alternately. - Requires 187.5MHz ADCs and DACs. - Pulse shaping generally spans 20symbols. 6. Option C- CAP/QAM-12 - X = 166.67MHz, NOT same as GMII - Y = 4Levels - Uses Two Hilbert-pair Pulse shaping transmit filters alternately. - Requires 250.0MHz ADCs and DACs. - Pulse shaping generally spans 20symbols. 7. Why Option A? - It is rooted in 802.3 Clauses - 5-level symbol encoding can be literally stolen from 100BASE-T2, Clause 32. - Same cabling, same symbol rate, same pulse shaping as 100BASE-Tx. Relevant specs can be reused from Clause 24, ANSI TP-PMD. - NRZ Pulse shaping used in 10BASE-T after Manchester Encoding, 100BASE-Tx after MLT-3 encoding - Minimum latency pulse shaping for bit-budget conscious CSMA/CD. - Simple low-latency receivers possible. Sophisticated, Complex, fractionally-spaced receivers possible too! - Excellent emissions/susceptibility tradeoff. - Obvious choice, provided it works well enough. 8. Why NRZ Pulse Shaping? 9. In Practice - WRONG QUESTION!!!!!!! - Everybody does it! Actual Question should be: HOW NRZ Pulse Shaping? 10. Option A: Enhanced Tx/T2 Proposal - 5-level symbols are fed to 5-level 125MHz DAC. - Minimum Latency approach. 11. Option B: CAP/QAM-25 - 5-level 125MHz symbols are first rate-converted and filtered to 128-level 187.5MHz samples and then fed to 128-level, 187.5MHz DAC. - 10Byte-Time Latency in transmit pulse shaping - 25% of Tx/Rx latency budget allowed for 1000BASE-T PHY. - Cause 187.5MHz 2Vptp high-frequency edges on output waveform. - High Frequency spectrum is far worse than NRZ/MLT-3. 12. Distilled 1000BASE-T Transmitter Question - In Option B transmitter (CAP/QAM), we expend - 25% of Tx/Rx latency budget on transmit pulse shaping - Eliminates trellis coding - 31-tap inphase/quadrature transmit filters - 128-level DAC instead of 5-level DAC - Create 2V ptp 187.5MHz high-frequency edges instead of 1V ptp 125MHz edges - What did we buy with this expenditure? - Built-in baseline wander compensation!! Yes. - Better emissions for the same susceptibility? - Overall much lower cost hardware for 1000BASE-T? - Ease of implementation of 100/1000 Combo solutions? - Better receiver jitter tolerance? 13. Baseline Wander in Enhanced Tx/T2 system - With random symbol generation - Worst-case RMS baseline wander is 0.8% of ptp voltage! - Killer packets are not an issue because of 33-bit scrambler length. 14. Why 5-level Encoding? 15. 5-level Encoding - Used in 100BASE-T2, Clause 32 of 802.3 standard. - 4-levels represent data. Extra level (ESC) used to transmit Start Stream Delimiter, End Stream Delimiter, Transmit Error, Idle/Data recognition etc. - Allowed symbol rate to be the same as MII clock rate in 100BASE-T2. - Allows symbol rate to be the same as GMII clock rate in 1000BASE-T. - Provides Trellis Coding and extra 5.2dB margin! - Close to optimum #levels for 1000BASE-T. 16. Properties of 100BASE-T2 5-level Encoding - Automatic Polarity Correction during idle. - Automatic pair swap correction during idle. - Automatic differential delay compensation during idle. - Ease of descrambler state recovery. - Guaranteed non-zero symbol once every two symbols during idle. - Instant (two-symbol) recognition of idle. - Instant (two-symbol) recognition of link partner's receiver status during idle. - Packet delimiters are better protected codes than normal data. 17. Principles of 100BASE-T2 5-level Encoding - All random bits needed are generated from one scrambler that is advanced one bit per symbol. - Partition 5-levels into two subsets: - X = {-1, +1} - Y = {-2, 0, +2[=ESC]} - Random sign inversion to remove DC disparity - Sense of sign inversion is reversed between data/idle. Thus, -2 during data is ESC during idle and vice-versa. - During idle, the only combinations allowed on Pairs A,B are: - XY on Pairs A,B - transmitted when scrambler bit is 1. - YX on Pairs A,B - transmitted when scrambler bit is 0. - Continuosly conveys pair identity, scrambler state, pair alignment to link partner - Odd Y symbol is inverse of previous even one. Guarantees that -2 is sent once every two symbols to ensure idle/data recognition. 18. Overview of Enhanced Tx/T2 proposal - "Dualized" 100BASE-T2 PCS - Use redundancy to do parity encoding - 100BASE-Tx PMA - Simple reuse of existing 100BASE-T standards to achieve 1000BASE-T! 19. Enhanced Tx/T2 Subset Mapping - A 1-D View - Subset D0 is {XYXY OR YXYX} on pairs A,B,C,D. - Subset D1 is {XYYY OR YXXX} on pairs A,B,C,D. - Subset D2 is {XYYX OR YXXY} on pairs A,B,C,D. - Subset D3 is {XYXX OR YXYY} on pairs A,B,C,D. - Subset D4 is {XXXX OR YYYY} on pairs A,B,C,D. - Subset D5 is {XXYX OR YYXY} on pairs A,B,C,D. - Subset D6 is {XXYY OR YYXX} on pairs A,B,C,D. - Subset D7 is {XXXY OR YYYX} on pairs A,B,C,D. 20. Idle Encoding - In 100BASE-T2, the idle codes are XY and YX. - In 1000BASE-T, we can use D0 for idle codes. - XYXY is sent if scrambler bit is 0. - YXYX is sent if scrambler bit is 1. - Ensures that in trellis coded version of 1000BASE-T, the parity encoder is in state 0 during idle. - Compatible with 100BASE-T2. - Guarantee that a dual-ESC code is sent once every two symbols during idle to distinguish idle from data. 21. Symbol Mapping - An Algorithmic View - 2LSBs + parity bit is used to select one of 8 subsets, Di. - 6MSBs (B7-B2) are used to select a point within subset as follows: - B7=0: Use Normal Data Code - B6=0: Use X-primary code - B6=1: Use Y-primary code - B5,B4,B3,B2 - select -1(X),-2(Y) or +1(X),0(Y) on pairs A,B,C,D respectively. - B7=1: Use Single ESC Data Code - B6,B5: Used to select position of +2[ESC] symbol (on which pair?) - B4,B3,B2 - select -1(X),-2(Y) or +1(X),0(Y) on non-ESC pairs. 22. Receiver Slicing Approach - On each pair, - Slice to X point with error Ex. - Slice to Y point with error Ey. - Without trellis coding, - Valid code must have an even number of X points. - Reverse mapping algorithm to read off the bits. - With trellis coding, - find nearest code point within each subset using XY pattern of subset - use as distance metric in Viterbi decoder - reverse algorithm to get inverse mapping from valid code to bits. 23. Packetized Trellis Codes - Idle encoding uses only D0 points - Data encoding uses all points - At end of frame, use two symbols to restore parity encoder states to 000 prior to sending ESD symbols. - Use current states of parity encoder as subset-selection bits and pick an invalid multiple-ESC code within that subset, for two cycles. - Ensures that at end of packet, Viterbi Decoder has prior knowledge of final state and can read off the residual symbols without SNR penalty. 24. Simulation Environment - Bob Campbell's Insertion Loss Curve - Echo Return Loss Curves from Bob Campbell. - NEXT Loss Curves from Bob Campbell - Dual 100KHz transformers with single-pole HPF model. - 100MHz 2nd order Butterworth receive anti-aliasing filter. - 16X Oversampling for analog signal calculations. - 4.0ns RC first-order exponential rise and fall times on NRZ pulse. - First order analog LPF with 3dB at 100MHz to account for transformer losses - 1.4dB loss at 62.5MHz - 4096-tap FIR filter calculations 25. The TABLE - 3dB design point Digital Transmit Filter: NONE D/A Resolution: 5levels D/A Clock Frequency: 125MHz Launch Level: 1V ptp Analog Transmit Filter: Single pole RC Analog Receive Filter: BW2 at 100MHz A/D Resolution: 5.5bit ideal A/D Clock Frequency: 125MHz Baseline Wander Circuit: Digital FFE-#taps: 10taps at 125MHz DFE-#taps: 8taps at 125MHz NEXT Cancellers: 20taps at 125MHz Echo Canceller: 80taps at 125MHz Viterbi Decoder: 15-stage Total Worst Case Latency: 35 Byte Times Uniform Jitter Tolerance for 0dB Margin: 1.4ns ptp Worst-Case Noise Immunity: 85mV ptp for 1V ptp launch level Estimated Gate Count: 230K gates Estimated WC chip Power: 3.1Watts Margin with WC FEXT: 2.5dB 26. The TABLE - 10dB design point Digital Transmit Filter: NONE D/A Resolution: 5levels D/A Clock Frequency: 125MHz Launch Level: 1V ptp Analog Transmit Filter: Single pole RC Analog Receive Filter: BW2 at 100MHz A/D Resolution: 7bit ideal A/D Clock Frequency: 125MHz Baseline Wander Circuit: Digital FFE-#taps: 14taps at 125MHz DFE-#taps: 12taps at 125MHz NEXT Cancellers: 80taps at 125MHz Echo Canceller: 120taps at 125MHz Viterbi Decoder: 15-stage Total Worst Case Latency: 35 Byte Times Uniform Jitter Tolerance for 0dB Margin: 1.8ns ptp Worst-Case Noise Immunity: 90mV ptp for 1V ptp launch level Estimated Gate Count: 390K gates Estimated WC chip Power: 4.3Watts Margin with WC FEXT: 7.0dB 27. Latency Budget Details Total Transmitter Latency: 8BT MII Interface: 3BT (assuming Option C GMII clocking) Scrambler+Encoder+Symbol Mapping: 3BT Analog Transmit Section: 2BT Digital Transmit Section: 0BT Total Receiver Latency: 27BT Analog Receive Section: 3BT ADC Output Register: 1BT FFE Group Delay: 3BT Slicer+Alignment: 3BT Viterbi Decoder+SSD/ESD detect: 15BT Descrambler + Symbol Decode: 2BT Total Tx+Rx Latency: 35BT Worst Case < 40BT allowed NOTE: All operations happen on Byte clock. 28. Charting a Solution for 1000BASE-T - Two main questions to answer: - Which digital transmit filter to use? - NONE? - STRONGLY RECOMMEND - CAP/QAM Inphase/Quadrature digital transmit filters? - How many levels? - 4 at 166.67MHz? - 5 at 125MHz? - STRONGLY RECOMMEND