GMII Timing Update




Asif Iqbal 
Berkeley Networks
Asif.Iqbal@BerkeleyNet.com


David Fifield
National Semiconductor

Jayant Kadambi
AMD





MAC to Long Haul Copper PHY Interface



* Use Source Synchronous Clocking for MAC to PHY and PHY to MAC data transfer.

* Use Rising Edge of GTX_CLK to launch data (TXD<7:0>) from MAC and Falling Edge of GTX_CLK to latch data in PHY.

* Synchronize TBC and GTX_CLK clocks in PHY. The two clocks have the same frequency but unknown phase relationship.
* 
* Use rising edge of RX_CLK to launch data (RXD<7:0>) from PHY and Falling Edge of RX_CLK to latch data in MAC.

MAC to SerDes Interface Timing



Parameters
Fast Path (ns)
Slow Path (ns)
Clock Insertion Delay in MAC
0.6
2.4
Clock to Data Out to SerDes including flop & output buffer delay in MAC driving 5pF or 10pF load capacitance.
1.3
4.2
Board Clock Skew
-0.1
0.1
Board Clock Delay to SerDes relative to MAC
-0.3
-0.2
Input Setup Time at SerDes including the input buffer delay and PLL skew

1.5
Hold Time at SerDes
1.5
















Silicon Vendor Timing Feedback


The following companies have validated the timing parameters based on their 0.35um technology capabilities:

* Lucent Technologies 
* LSI Logic
* National Semiconductor
* AMD
berkeley
networks



IEEE 802.3z Task Force	2	03/09/97