Copper PHY Evaluation Criteria

			Sailesh K. Rao
		   Silicon Design Experts, Inc.
                     Ph: (908)-972-0707 x11
                   e-mail: sailesh@sde.com

		    with contributions from
		        John Creigh, IBM
		  John Seimon, The Seimon Company
		       Chris DiMinico, DEC
		   Victor Renteria, Pulse Engg.

                   IEEE 802.3 GTF, Couer D'Alene, ID.
                       September 9-11, 1996.


1. Objectives
   
 - Create a common set of evaluation criteria for the various Copper PHY 
   proposals for 1Gb/s over 4-pair 100m UTP-5

    - to compare implementation complexities for like performance
    - to ensure feasibility of proposed solutions
    - to ensure end-to-end system level forethought in the proposals
    - to anticipate and eliminate unpleasant surprises in the field
    - to facilitate 100/1000 designs

2. Criterion 1- Attenuation

 - Show operation over 100m worst-case UTP-5 cabling attenuation
   
   - A(f) - (1.0 + 0.003*[T-20]) * (0.3 + 1.967sqrt(f) + 0.04f + 0.05/sqrt(f)) dBs

   - [Figure of worst-case attenuation]

   - Contribution of measured worst-case attenuation solicited

3. Attenuation Roughness?

 - Causes:

   - Non-uniformity in characteristic impedance of UTP-5 wiring
   - Random reflection losses
   - Increases in prominence at higher frequencies
   - Might require longer DSP-based line equalizers for schemes that use
     high-frequency signalling
   - Use models or "worst-case" measured?

 - Model:

   [Figure of non-uniform transmission line model]

4. Criterion 2- self NEXT

 - Show operation in the presence of three worst-case self-NEXTs.
   
   - NEXT envelope(f) = 27.1 - 16.8*log10(f/100) dBs

   - [Figure of three self-NEXT curves]

   - SDE NEXT curves generated using Ungerboeck NEXT model

5. Criterion 3- Echo Return Loss

 - Show operation in the presence of worst-case Echo Return Losses.

   - ERL_Envelope(f) = 14.0 dB                  f<20MHz
                       14.0 - 10log10(f/20) dBs f>20MHz

   [Author's note: Based on ANSI X3.263-1995, this should be modified to:
     ERL_Envelope(f) = 13.0dB                 f<30MHz
                     = 13.0-20log10(f/30) dB  30MHz<f<60MHz
                     = 7.0dB                  f>60MHz 
   ]

   [ Figure of SDE ERL curves]
  
   - SDE ERL curves generated using a variation on Ungerboeck's NEXT model.

6. Modeling Echo Return Loss

 - Components
   
   - Hybrid Return Loss - can be optimized for different frequencies
   - Return Loss from impedance mismatches at near-end connectors
   - Return Loss from impedance mismatches at far-end connectors
   - Structural Return Loss of the wiring

   [ Figure of Return Loss components ]

   - Worst-case ERL is a function of the signalling proposal

7. Compliance with EMC Requirements
  
 - Compare transmit spectrum with 100BASE-Tx
    
    - 100BASE-Tx will be fallback mode anyway

 - If all 4 pairs of UTP-5 cabling are used, must consider power sum of
   4 transmit signals

    [Figure of 100BASE-Tx spectrum]

8. EMI Susceptibility Requirements

 - Plot sinusoidal noise tolerance as a function of frequency assuming
   no echo, no self-NEXT and adaptation is disabled.

 - Is ability to do automatic recovery sufficient?

   [Figure of Crane Test set-up]

9. Complexity Criteria

 - For achieving BER of 10^-10 under worst-case conditions:
  
   - DSP complexity for Equalizationo and Echo/self-NEXT cancellation
   - Complexity of analog filters, line drivers
   - A/D Converter requirements
   - D/A Converter requirements
   - Can clock recovery be done easily?

 - Can the above be achieved when cable is at 60 deg. C?

   - A low complexity solution that achieves BER of 10^-10 at high 
     temperatures and under worst-case conditions WINS hands down?

10. Other Considerations

 - Ease of Performance Monitoring (during idle, as in 100BASE-T2)
 - Automatic polarity detection and correction
 - Automatic pair-swap detection and correction
 - Automatic Receiver OK/Not_OK indication
 - "Compatibility" with 100BASE-T PHY designs
 - Meets Latency Budget?