Re: [802.3_4PPOE] PSE current limiting (ILIM / TLIM)

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Hi Lennart,

Thanks,

Please send me the latest baseline and see more below.

Yair

From: Lennart Yseboodt [mailto:lennart.yseboodt@xxxxxxxxxxx]
Sent: Monday, May 14, 2018 2:19 PM
To: STDS-802-3-4PPOE@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_4PPOE] PSE current limiting (ILIM / TLIM)

EXTERNAL EMAIL

Hi all,

Updated text for PSE current limiting.

Yair - there is no basis in our draft, or in Clause 33 to conclude that current limiting only applies to positive transients.

Yair: Lennart, normally for most of the spec items, we don’t specify why we did it. We just specify the requirement.

The way to know why we did it, is to look at the history, presentations or the guys the generate this spec. So, the reason why we generate this spec was to address the case that PSE switched from its power supply to a buckup supply. In this case the backup supply has a higher voltage than the PSE power supply which result in current transient due to Cpd*dv/dt where (dv/dt) is positive.

If it was negative voltage slope, at this time the current would be zero due to the PD diode reverse bias.

Now, thinking about it with ideal diode bridge, it looks to me that with negative dv/dt the current will be increase too since it is a MOSFET that is always ON è no reverse voltage è if voltage is dropping, current will increase.

Bottom line, in 802.3bt spec in order to support diodes and ideal diode bridges, the PSE should support transients for TLIM regardless of the dv polarity.

Summary:

The text in page 183 line 83:” The PSE shall limit the pairset current to ILIM-2P for a duration of at least TLIM. The cumulative duration of the current limit event may be measured with a sliding window of at most 1 second width.” Should stay as is.

The text in page 184 line 1: “If a short circuit condition is detected on a pairset, power removal from that pairset shall begin within TLIM as defined in Table 145–16. If IPort-2P exceeds the PSE lowerbound template, the PSE output voltage may drop below VPort_PSE-2P min.” is different from the above. This one is talking about short circuit and the above is addressing transients. So you need just to clarify in this text that this is not a VALID transient condition.

Clause 33 says:

The statements on page 183/26 and 184/1 are literally the inverse of each other, they cannot both be met.

What I think you're saying is that because transients longer than 250uS have to meet the VPort_PSE-2P specification, then for the bulk of the TLIM time, in a compliant system, it can't happen that VPSE is outside of this range?

Yair: Correct.

Note however that after a transient (however short) the PD has up to TLIM before it needs to meet the operating power limits and during this time there is a bulk cap voltage difference that needs to be resolved.

Hence, for the system spec to work, we do need the PSE to current limit for a duration of at least TLIM min, when the PSE voltage >Vtran-2P.

Kind regards,

Lennart

On Tue, 2018-04-17 at 11:44 +0000, Lennart Yseboodt wrote:

Hello,

Please see proposed baseline for PSE current limiting.

Kind regards,

Lennart

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