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Re: [HSSG] Yet another topic for consideration - bit parallel

Title: Yet another topic for consideration - bit parallel
What I'd love to have join in this conversation is someone with recent experience in the memory space.  DDR, with its many sequels, now with the follow-on complementary AMB and FBDIMM, represent a great deal of time on grade of short distance high bandwidth source synchronous interfaces who's tolerance for skew and differential delay is bounded by the PCB environment in which they live.
This highly constrained environment creates opportunities for creativity.  It may be the same interface as the line, but given the significantly different constraints, may not.
Regards, Bill
Bill Woodruff
Aquantia - VP Marketing
408 228 8300 x202
(c) 408 582 2311

From: Brad Booth [mailto:bbooth@xxxxxxxxxxxxx]
Sent: Wednesday, August 02, 2006 8:11 AM
To: STDS-802-3-HSSG@xxxxxxxxxxxxxxxxx
Subject: Re: [HSSG] Yet another topic for consideration - bit parallel

The 802.3 MAC specification is bit serial.  If there are no unique features added (e.g. IPG stretching for WIS mode), modifications for speed are fairly straight forward (thanks to Shimon Muller and others for making the 802.3 MAC speed agnostic).
That being said, implementations of the 802.3 MAC are rarely bit serial.  Where that usually shows up in an 802.3 specification is the MAC/PLS service interface, also known as the MAC-PHY interface.  These interfaces, such as MII, GMII and XGMII, are all source synchronous single-ended interfaces that hint at the MAC implemention.  During 802.3ae, the realization that a 74-bit interface between a MAC and a PHY was inefficient and the differential XAUI came into existence.  In 10GbE, both interfaces where implemented by vendors, but XAUI was definitely the interface of choice.  The question this time around is does the HSSG create an objective for a source synchronous single-ended interface (which hints at the MAC implementation) or does the HSSG have only an objective for a differential interface (which will likely be the implemented interface).

From: Kevern, James D [mailto:james.kevern@xxxxxxxxxxxxxxxxxxx]
Sent: Wednesday, August 02, 2006 7:05 AM
To: STDS-802-3-HSSG@xxxxxxxxxxxxxxxxx
Subject: [HSSG] Yet another topic for consideration - bit parallel

Along with a previous suggestion that we become more educated on the problems associated with n x 10G LAG implementations, I, for one, would like to better understand the concerns regarding what I'll call bit parallel vs serial implementations.  There was an earlier post indicating MAC implementations might be in the order of 64 wide, maybe even 128.  So at the one extreme, one could envision a parallel connection 64 wide, at the other extreme is time division multiplexing this down to a single serial stream.  Note, that for this discusion, it does not matter whether the parallel paths are accomplished by individual cables, individual fibers in one cable, different wavelengths on a single fiber, or even individual traces on a backplane.  As has been mentioned, there are various possibilities in between the extremes, such as 10x 10 Gig, N x M, etc.

There are, of course, the obvious cost and reliability issues of number of sources, detectors, fibers, connectors, space constraints, etc.  But what about performance issues such as latency and throughput.  How would bit parallel differ from LAG?  Are there other issues as well?

This is a specific case of what could be considered a broader topic related to how we organize our work.  In addition to, as Menachem suggested, prioritizing application spaces, perhaps building a knowledge foundation, whether through postings here, tutorial presentations, links to web sites, etc. could be an early part of the effort.