| Thread Links | Date Links | ||||
|---|---|---|---|---|---|
| Thread Prev | Thread Next | Thread Index | Date Prev | Date Next | Date Index |
|
Jim, Regarding your question on serial
implementations: The state of the art, as far as I know, on
higher speed serial transmission modules which are commercially available today,
is 40 Gb/s (see OC-768 ports on core routers). A typical device of this type, used for
relatively short distances, has an SFI-5 interface (OIF spec) which is 16 x 2.5
Gb/s with the proper de-skew mechanisms on the system side, connecting on a PCB
to a SONET framer (or in principle could connect to an Ethernet MAC chip). On
the optical side it is 40 Gb/s serial. Inside such modules you will typically
find Silicon-Germanium (SiGe) Serializer and Deserializer chips which
have a 40 Gb/s electrical interface. The serial 40 Gb/s Tx electrical signal drives
an optical modulator (e.g. Electro-Absorption-Modulator or EAM) and hence
generates the serial optical bit stream at 40 Gb/s. The 40 Gb/s optical Rx
signal goes into a PIN diode which connects electrically to a preamplifier or
directly into the Deserializer. Modules of this type usually run with NRZ
data. Some of these modules can run as high as 43 Gb/s which allows the application
of Forward Error Correction techniques prior to the SFI-5 interface on the
system side (which becomes 16 x 2.7 Gb/s) and thus adding 3 – 6 dB to the
link budget (depending on the type of FEC used). The market inputs we received in the
pre-CFI phase indicated strong preference for HSSG to go higher than 40Gb/s. If
that input will stay consistent in the next few months we will have to go to “multiple
lanes” (Physical Link Aggregation). The question is how many lanes and at
what speed.... Regards, Menachem From: Kevern, James D
[mailto:james.kevern@xxxxxxxxxxxxxxxxxxx] Along
with a previous suggestion that we become more educated on the problems
associated with n x 10G LAG implementations, I, for one, would like to better
understand the concerns regarding what I'll call bit parallel vs serial
implementations. There was an earlier post indicating MAC implementations
might be in the order of 64 wide, maybe even 128. So at the one extreme,
one could envision a parallel connection 64 wide, at the other extreme is time
division multiplexing this down to a single serial stream. Note, that for
this discusion, it does not matter whether the parallel paths are accomplished
by individual cables, individual fibers in one cable, different wavelengths on
a single fiber, or even individual traces on a backplane. As has been
mentioned, there are various possibilities in between the extremes, such as 10x
10 Gig, N x M, etc. There
are, of course, the obvious cost and reliability issues of number of sources,
detectors, fibers, connectors, space constraints, etc. But what about
performance issues such as latency and throughput. How would bit parallel
differ from LAG? Are there other issues as well? This
is a specific case of what could be considered a broader topic related to how
we organize our work. In addition to, as Menachem suggested, prioritizing
application spaces, perhaps building a knowledge foundation, whether through
postings here, tutorial presentations, links to web sites, etc. could be an
early part of the effort. Jim Kevern ( phone:
717-986-5701 . Mailing Address:
Shipping Address: |