Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY
Hi, Ragnar,
In DATA_MODE, the MASTER and SLAVE are fully timing-locked—both symbol and RS-FEC frame timing stay aligned. This allows both sides to know exactly where each received frame starts and ends, with no cycle slipping between bursts. It works similarly to EEE mode in 802.3bp/ch, which many are familiar with.
As for delay_count, since the Task Force hasn’t finalized the channel delay, we’ve allowed a range of 0 to 31 for now. This range can be narrowed once the actual delay values are determined.
Wei
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