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Hi Wei, Thank you for your response. I think that some clarification of the purpose of SILENT1 would help implementers. I did not fully understand it’s purpose before seeing your explanation. I had assumed that SILENT1 related to timing alignment
of signals when changing from symmetric training (SEND_TS) to asymmetric training (SEND_TA). During this transition the Slave has to almost double the duration of its transmit burst, but also move its start of transmission about 4000ns earlier in the TDD cycle.
Even in my simplified simulation (only simulating the state transitions, not the actual signals on the line), this could be very challenging and error prone without SILENCE1. While I think that clarifying the purpose of SILENCE1 would be beneficial, I don’t think it is enough by itself, because as long as config_timer_done can transition the Slave from SILENT1 to SILENT0, you will
have a potential problem with the statup sequence. By the way, another strange behavior I saw in my TDD state diagram simulations was if the Master would set loc_rcvr_status0 to NOT_OK at the very end of the COUNTDOWN0 state. In
this case the Master would transition to SILENT0 and then directly to TRAINING0, while Slave would transition to SILENT1. In this case the Master would be sending SEND_TS with
4586.67ns transmit burst, while the Slave was expecting the Master to be transmitting SEND_TA with 560ns transmit bursts. I still don’t have a simulation that handles this correctly, without breaking something else. I wonder
if you have seen this case in your simulations as well. Ragnar From: Wei Lou <000047a3c8c56bbe-dmarc-request@xxxxxxxxxxxxxxxxx>
Hi, Ragnar, The SILENT1 state is proposed by several of the TDD supporters, to allow some extra config/preparation time for the SLAVE to switch its transmit signal
from 3Gsps(PAM2) to a final symbol rate of 6 Gsps PAM2. During this time, the ZjQcmQRYFpfptBannerStart
ZjQcmQRYFpfptBannerEnd Hi, Ragnar,
The SILENT1 state is proposed by several of the TDD supporters, to allow some extra config/preparation time for the SLAVE to switch its transmit signal from 3Gsps(PAM2) to a final symbol rate of 6 Gsps PAM2. During this time, the MASTER switched to the transmission of 3Gsps PAM2 SEND_TA TDD cycles without interruption. The MASTER RX should expect the SLAVE TDD transmission may stop briefly ( for a few bursts), before SLAVE starts to transmit the High Rate TDD PAM2 signals( SEND_TA TDD cycles). When SLAVE TX doesn't need to switch rate, it could just pass through SILENT1 state and start SEND_TA transmission( with SEND_TA TDD timing).
The config_timer is proposed to specify the maximum time allowed for SLAVE to reconfigure its transmit circuit. So the expiration of this timer means something is wrong. SLAVE goes back to SILENT0 state, while MASTER stays in TRAINING1 state, until its link_inhibit_timer expires, as what you described. When MASTER enters TRAINING0 state, SLAVE re-achieves its loc_rcvr_status=OK, it enters TRAINING0 state, while restarting its link_inhibit_timer. If your concern is that the previous expiration of link_inhibit_timer may bring the SLAVE from TRAINING1 state back to DISABLE_TRANSMITTER state, we can add a short timer (similar to min_wait_timer, value TBD) to stay in TRAINING0 state, until SLAVE restart link_inhibit_timer.
For SLAVE, the actual exit condition from SILENT1 to TRAINING1 is loc_rcvr_status=OK and transmit_config_done/SEND_TA transmit ready. If this could help to clarify the intention of SILENT1 state, I am OK to add this signal into the proposal.
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