Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY

[Ragnar Jonsson <rjonsson@xxxxxxxxxxx>]

Hi Mehmet and Wei,

 

I agree that it makes sense to defer discussion until things are defined in the text proposals. However, there is already a description in the New-TDD text proposal from New Orleans related to my question.

 

I had been making the following assumptions:

1. The low data rate transmitter is typically the MASTER (see justification below)
2. The SLAVE derives its clock from the MASTER transmit signal (see justification below)

 

Wei’s earlier explanation included the key statement “In SEND_TA, In the high-speed direction, the QUIET period is very short (773.3 ns), so the signal eye remains open after QUIET, and there’s no echo, therefore fast CDR can be used to quickly adjust timing loops.”

 

It looks to me like the statement that the MASTER can quickly adjust its CDR is not consistent with my assumption that the SLAVE derives its clock from the MASTER transmit signal, and not the other way around. What am I missing?

 

The following are justifications for my two assumptions above, based on statements in the New Orleans New-TDD text proposal.

 

The New-TDD text from New Orleans states on page 41:

A timer used to control the duration for the Transmission of asymmetric training sequence during DATA state of PHY control state. A value of 560 ns for the MASTER PHY and a value of 8826.67 ns for the SLAVE PHY.

 

I understand this description to mean that the MASTER is the low data rate transmitter. This is consistent with my assumption #1.

 

The New-TDD text from New Orleans states on page 52:

When the PMA_CONFIG indication parameter config is MASTER, the PMA Transmit function shall source TX TCLK from a local clock source while meeting the transmit jitter requirements of 200.x.2.3(TBD). The MASTER-SLAVE relationship shall include loop timing. If the PMA_CONFIG indication parameter config is SLAVE, the PMA Transmit function shall source TX TCLK from the recovered clock of 200.4.2.8 while meeting the jitter requirements of 200.x.2.3(TBD)

 

I understand this description to mean that the SLAVE shall source it’s transmit clock from a clock recovered from the MASTER transmit signal. This is consistent with my assumption #2.

 

The only way I can interpret these statements is that the SLAVE has to recover its clock from the 560ns burst that come every 9600ns (see Table 200-7 on page 34). This is why I made my earlier statement that “it is not clear to me that we can assume that the Master and Slave are perfectly timing locked.”

 

Ragnar

 

From: Mehmet Tazebay <mehmet_tazebay@xxxxxxxxx>
Sent: Thursday, July 24, 2025 9:53 AM
To: Ragnar Jonsson <rjonsson@xxxxxxxxxxx>
Cc: STDS-802-3-ISAAC@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY

 

Hi Ragnar, As Wei mentioned in his emails, the TDD proposal provide a baseline for the main blocks, state machines and signal definitions. Some implementation related details such as clock stability and jitter requirements are not discussed

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Hi Ragnar,

 

As Wei mentioned in his emails, the TDD proposal provide a baseline for the main blocks, state machines and signal definitions. Some implementation related details such as clock stability and jitter requirements are not discussed and identified for both proposals. Therefore, we will defer these discussions when we get to that point.

 

Mehmet

On Jul 22, 2025, at 6:39 PM, Ragnar Jonsson <rjonsson@xxxxxxxxxxx> wrote:



Hi Wei,

 

Thanks again for the prompt response.

 

For me the key sentence in your response is “In SEND_TA, In the high-speed direction, the QUIET period is very short (773.3 ns), so the signal eye remains open after QUIET, and there’s no echo, therefore fast CDR can be used to quickly adjust timing loops.”

 

I had been making the following assumptions:

1. The low data rate transmitter is typically the master
2. The slave derives its clock from the master transmit signal

 

The sentence I quoted appears to imply that the high data rate receiver is tracking the clock of the high data rate transmitter. This would not be consistent with my two assumptions above.

 

Are my assumptions that the slave tracks the master clock (and not vice versa) incorrect for the New-TDD?

 

Ragnar

 

From: Wei Lou <000047a3c8c56bbe-dmarc-request@xxxxxxxxxxxxxxxxx>
Sent: Tuesday, July 22, 2025 6:12 PM
To: STDS-802-3-ISAAC@xxxxxxxxxxxxxxxxx
Subject: Re: [802.3_ISAAC] [EXTERNAL] Re: [802.3_ISAAC] Question on Baseline Text Proposal for TDD Based 802.3dm PHY

 

Hi Ragnar, I believe this thread is mainly focused on the text proposal, including block diagrams and signal definitions. So it might not be the best place to dive into the training process and related technical details like clock stability

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Hi Ragnar,

I believe this thread is mainly focused on the text proposal, including block diagrams and signal definitions. So it might not be the best place to dive into the training process and related technical details like clock stability or jitter requirements. Those topics would be better suited for a separate presentation.

That said, let me briefly address your question.

While the TDD proposal shares some similarities with the EEE LPI operation in 802.3bp/ch, there are advantages due to the nature of the TDD approach.

After the SEND_TS (symmetric training) phase, the SLAVE is frequency-locked to the MASTER clock. This means the initial PPM offset during SEND_TA is much smaller—typically in the low single digits, not 50 ppm—because otherwise the SLAVE wouldn’t maintain loc_rcvr_status = OK during SEND_TS.

In SEND_TA, In the high-speed direction, the QUIET period is very short (773.3 ns), so the signal eye remains open after QUIET, and there’s no echo, therefore fast CDR can be used to quickly adjust timing loops. Therefore, your concern about needing 8 frames (as in 802.3ch, PAM4) to achieve symbol/frame sync before data traffic doesn’t apply here. After the initial PAM2 refresh header, the eye remains wide open through the PAM4 RS-FEC frames.

In the low-speed direction, the MASTER uses PAM2 modulation, which is more directly comparable to 802.3ch’s PAM2 refresh/quiet cycles. In 802.3ch, symbol and frame sync is maintained even with a refresh/quiet ratio of 1:95. In our TDD proposal, the refresh header to QUIET ratio is 1:42, and the total TX(burst) time to QUIET ratio is 1:16. With no echo and similar timing behavior, we believe the proposed TDD scheme can maintain sync just as effectively. The new TDD proposal QUIET time is only around 9 us, which is a fraction of the 802.3 ch at similar symbol rate.

Wei

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