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[802.3_POPI] POPI Interim Meeting for June 9, 2026 is CANCELLED

As I have not received any request for presentation time according to the request below, we have no agenda and therefore tomorrow's meeting is cancelled. 

Jason Potterf
Principal Hardware Engineer, Cisco
Treasurer, IEEE 802 LMSC
Chair, IEEE 802.3dq Pin-Optimized PHY Interface Task Force
From: Jason Potterf (jpotterf) <0000142267c8912c-dmarc-request@xxxxxxxxxxxxxxxxx>
Sent: Tuesday, June 2, 2026 6:44 PM
To: STDS-802-3-POPI@xxxxxxxxxxxxxxxxx <STDS-802-3-POPI@xxxxxxxxxxxxxxxxx>
Subject: [802.3_POPI] POPI Interim Call for Presentations
 
As previously announced, we are scheduled to meet next Tuesday, June 9th. The presentation request deadline is Friday, June 5th. If I do not receive any presentation requests, the meeting will be cancelled for lack of agenda. 

I have been informed that there will not be presentations from any of the three presenters from our prior meetings. I am calling upon the other Task Force members to consider addressing one of the open questions we collected during our previous meeting; even a brief presentation that suggests an answer or solution would be welcome.

For your convenience, the list of open questions follows taken from https://www.ieee802.org/3/dq/public/2026-05-14/POPI_Agenda_2026-05-14_v03.pdf

  • Where should we use 8b/10b?
  • Where should we use 64b/66b?
  • How should we send link status?
  • What should the lowest active speed be for non-SerDes interfaces?
  • What should the lowest active speed be for SerDes interfaces?
  • What sideband payloads have we missed and what are their latency and bandwidth requirements?
  • What per-packet metadata payloads have we missed and what are their size and frequency characteristics?
  • What are the requirements around the PLS_CARRIER and PLS_SIGNAL signals at the PLS Service interface?
  • How do we support PLCA without COL/CRS?
  • What other facilities do we need to provide to support TSN and similar technologies?
  • How should we structure our clause(s) for baseline text?
  • How much of GMII/XGMII might we be able to leverage for baseline text?
  • How shall we byte stuff the channel to minimize buffer requirements for faster-than-necessary channels?
  • How do we optimize our choice of clock frequencies and SerDes speeds (e.g. make use of commonly available components in the market)?
  • For our electrical interfaces, how much should we specify? For instance, if we specify voltages, which ones?

Thanks in advance for your contributions!

Jason Potterf
Principal Hardware Engineer, Cisco
Treasurer, IEEE 802 LMSC
Chair, IEEE 802.3dq Pin-Optimized PHY Interface Task Force

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