Dynamic Metroring

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Dear members of IEEE 802.17

We,

the Institute of Communication Networks at Vienna University of Technology, Vienna, Austria,

the Bocholt Institute of Technical University Gelsenkirchen, Bocholt, Germany,

and Datentechnik, Vienna, Austria

would like to present in the near future the arcitecture and the operation principles of a dynamic packet ring comprising all features that IEEE 802.17 RPRWG intends to standardize. Its design also includes a MAC protocol that features local fairness, thus effectively coordinating the ring access of only those nodes that use the same links for their packet transfers. Therefore, all nodes that do not interfere are not throttled in their performance as is in the case of global fairness mechanisms ( e.g. ATMR, Metaring and CRMA-II). Performance studies also have been done.

We only recently learned about the IEEE 802.17 initiative and we therefore could not receive a presentation slot at the March 2001 meeting. At the next interim meeting in May 2001 we will therefore give presentations on (1) the architecture and the principles of operation, (2) the MAC-protocol, and (3) MAC-protocol performance.

The dynamic ring we will present exhibits the following features:

- Single, dual or multiple ring topologies with shot-cuts where appropriate

- Combined packet, cell and circuit switching

- Handling of asymmetric traffic flows

- Combined single and multcast operation

- QoS handling of flows with respect to throughput, delay and system availabilty

- No packet loss on the ring

- No packet loss due to destination port blocking

- Complete dynamic use of the bandwidth on each link of the ring

- Three traffic classes on the ring: SYN, ASYN1 and ASYN2

- Slotted transmission structure with buffer insertion to handle variable length packets

- Destination removal of slots

- Preemptive hierarchy of the ring traffic classes on slot boundaries

- Further access right distictions within the tree ring classes are handled above the MAC

- Inherently not more than 3 x 125 microseconds delay jitter for circuit connections (SYN traffic)

- Guaranteed delay bounds for packet/cell switching of the high-priority class ASYN1

- MAC addressing scheme incorporates ring nodes and all ports attached to the nodes

- Simple distributed set-up of circuit-switched channels after one ring roundtrip

- No fixed position of the SYN-slots of a channel within the framing period of 125 microseconds

- Immediate reuse of unused SYN-slots by other nodes

- Automatic protection switching upon link or node failures

- Scalabity of performance and node/port numbers by paralell rings and partial node-bypassing

- Transmission links between nodes may use different technologies (e.g. Gbe, SDH) and different bit rates

- Paralell rings may be multiplexed electronically (SDH hierachy) or optically (WDM)

- Designed for fast and efficient hardware implementations

- Possibility to combine low- and high-performance nodes attached to single/dual/multiple rings

Our background on slotted rings goes already back to the time we, Prof. Wolfram Lemppenau and myself, were at the IBM Zurich Research Laboratory from 1984 to 1996. We prototyped the Gigabit/s LAN called CRMA (Cyclic Reservation Multiple Access) in 1989/1990 and designed the MAC-protocol CRMA-II in 1990/1991 with partial prototyping in the following years. We have also been active in IEEE 802.6 and the ATM-Forum

With best regards

Harmen R. van As