IEEE 802 P802

IEEE 802.3 400 Gb/s Ethernet Study Group


"Logic" Ad Hoc Area


Oct 23, 2013 Teleconference

Unapproved Meeting Notes
    24-Oct 13  (117k)
Mark Gustin Xilinx
A 400GbE PCS Option
    23-Oct 13 (213k)
  
Mark Gustlin
Gary Nicholl
Dave Ofelt
Jerry Pepper
Andre Szdzepanek
Tongtong Wang
Xilinx
Cisco
Juniper
Ixia
Inphi
Huawei
Error performance objective for 400GbE
    23-Oct 13 (66k)
Pete Anslow Ciena
400GbE PCS Direct Coding Analysis
    23-Oct 13 (311k)
Haoyu Song
Wenbin Yang
Tongtong Wang
Huawei
     

August 20, 2013 Teleconference

Approved Meeting Notes
     24-Oct 13 (116k)
Mark Gustlin Xilinx
FEC/ Architecture/Extender Sublayer
     20-Aug-13 (898k)
John D'Ambrosia Dell
400GbE PCS Architectural Requirements
     20-Aug-13 (150k)
Mark Gustlin
Chris Cole
Pete Anslow
John D'Ambrosia
Xilinx
Finisar
Ciena
Dell
16 ‘v’ 80 PCS Lanes for 400GbE- An implementer's Perspective
    20-Aug-13 (255k)
Cedrik Begin
Gary Nicholl
Cisco
     

August 7, 2013 Teleconference

Approved Meeting Notes
     20-Aug 13 (109k)
Mark Gustlin Xilinx
Error Performance objective for 400GbE
     07-Aug-13 (121k)
Pete Anslow Ciena
400GbE BER Objective from the Perspective of MTTFPA
     07-Aug-13 (666k)
Wenbin Yang
Tongtong Wang
Haoyu Song
Huawei
     

June 26, 2013 Teleconference

Approved Meeting Notes
    07-Aug 13 (109k)
Mark Gustlin Xilinx
BER Objective format for 400GbE
    26-Jun-13 (110k)
Pete Anslow Ciena
Multi-rate support in 400GbE Logic Layer
     26-Jun-13 (637k)
Xinyuan Wang
Tongtong Wang
Wenbin Yang
Suping Zhai
Huawei
400GE Lane Configurations vs FEC Options
    26-Jun-13 (144k)
Zhongfeng Wang
Ali Ghiasi
Broadcom
    

June 7, 2013 Teleconference

Approved Meeting Notes
    26-Jun 13 (198k)
Mark Gustlin Xilinx
400GbE PCS Architectural Options
    12-Jun-13 (138k)
Mark Gustlin Xilinx
Forward Error Correction for 400G: Initial Thoughts
     12-Jun-13 (297k)
Stephen Bates PMC Sierra
    

Last Update: 19-Jun 2017

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