IEEE 802 P802

IEEE P802.3bs 200 GbE & 400 GbE Task Force

"Logic" Ad Hoc Area

March 9, 2017 Teleconference
Unapproved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Proposed restricted muxing rules	Kapil Shrikhande	Innovium
Impact of clock content on the CDR with proposed resolution	Ali Ghiasi Phil Sun Xiang He Xinyuan Wang	Ghiasi Quantum Credo Huawei Huawei
Proposed FEC degrade signalling changes Proposed FEC degrade signalling changes (text for changes)	Steve Trowbridge	Nokia

March 2, 2017 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Possible 7b scrmabler text changes	Mark Gustlin	Xilinx
Generating variable transition density patterns	Ali Ghiasi

February 16, 2017 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Restricted muxing update	Mark Gustlin Dave Ofelt Gary Nicholl Kapil Shrikhande	Xilinx Juniper Cisco Innovium
4 lanes muxing limited clock content analysis	Oded Wertheim	Mellanox
Impact on transition density on CDR	Ali Ghiasi

January 26, 2017 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Posssible solutions for the clock content issue	Mark Gustlin	Xilinx
Restricted muxing option	Mark Gustlin Dave Ofelt Gary Nicholl Kapil Shrikhande	Xilinx Juniper Cisco Innovium
On clock content issue over four lane interleaving	Ryan Wong Eric Baden Rob Stone	Broadcom

October 27, 2016 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
200GbE aklignment marker characteristics	Pete Anslow	Ciena
SSPRQ generation SSPRQ test pattern	Pete Anslow	Ciena
Autocorrelation of PRBS13Q	Yasup Hidaka	Fujitsu

April 28, 2016 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
PreFEC BER Signaling Features	Dave Ofelt	Juniper
SSPRQ test pattern presentation SSPRQ test pattern	Pete Anslow	Ciena
400GbE AMs revisited	Pete Anslow	Ciena

February 23, 2016 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Proposed MAC and PCS sublayer delay	Mark Gustlin	Xilinx
AMP_Valid and PCS_Lane TBDs	Mark Gustlin	Xilinx
Skew in 400GbE	Mark Gustlin	Xilinx
Alignment Marker Format Updates	Adrian Butter	Globalfoundries
400GbE AMs revised proposal	Pete Anslow	Ciena

February 9, 2016 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Proposed AM Format	Mark Gustlin	Xilinx

January 8, 2016 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
400GbE AMs revised proposal	Pete Anslow	Ciena
Pre-FEC BER Monitoring and signaling	Dave Ofelt	Juniper

December 11, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
FEC Modes	Phil Sun	Credo
Toward 400GbE AMs and PAM4 test pattern characteristics	Pete Anslow	Ciena
Marker Lock/Unlock Schemes for 400GE	Zhongfeng Wang	Broadcom

October 23, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
FEC codeword filling performance	Pete Anslow	Ciena
Toward convergence of FEC interleaving schemes for 400GE	Zhongfeng Wang	Broadcom

August 25, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
FEC codeword interleaving schemes	Pete Anslow	Ciena
Toward convergence of FEC interleaving schemes for 400GE	Zhongfeng Wang	Broadcom

June 29, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Update and further study on FEC architectural proposal	Xinyuan Wang Tongtong Wang	Huwaei
400G FEC complexity discussion	Tongtong Wang Xinyuan Wang	Huwaei
Further Analyses of Reducing Complexity for Data Alignment	Zhongfeng Wang	Broadcom

June 19, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
400GE FEC Implementation	Martin Langhammer	Altera
Considerations for Breakout	Martin Langhammer	Altera
1x400G vs. 4x100G FEC Implications	Bill Wilkie	Xilinx
Analysis on 400G FEC Architecture	Phil Sun	Marvell

April 27, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Investigation on Technical feasibility of FEC Architecture with 1X400Gbps or 4X100Gbps	Xinyuan Wang Tongtong Wang Wenbin Yang	Huawei
Wander in 400GbE Transcoding Link	Xinyuan Wang Tongtong Wang Zhijun Li	Huawei

February 17, 2015 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Logic Big Ticket Items	Mark Gustlin	Xilinx
Proposal for 400GbE FEC Architecture	Xinyuan Wang Tongtong Wang Wenbin Yang	Huawei

December 2, 2014 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Simplified Transcoding Scheme	Zhongfeng Wang	Broadcom
Further analysis for distributed MLG for 400GEl	Zhongfeng Wang	Broadcom
Investigation on technical feasibility of stronger RS FEC for 400GbE	Xinyuan Wang Tongtong Wang Wenbin Yang	Huawei

October 21, 2014 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
FEC Architecture	John D'Ambrosia Pete Anslow Mark Gustlin Adam Healey David Law Gary Nicholl Dave Ofelt	Dell Ciena Xilinx Avago HP Cisco Juniper
FEC core area comparison and model	Martin Langhammer	Altera
FEC Considerations for 400GE and Beyond	Martin Langhammer	Altera
FEC Structure for 400GbE	Zhongfeng Wang	Broadcom

July 1, 2014 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
FOM Bit Mux, Architecture, Challenge and Solution	Xinyuan Wang Tongtong Wang Wenbin Yang	Huawei
FEC considerations for 400GbE	Zhongfeng Wang	Broadcom
OTN Support	Steve Trowbridge	ALU

April 23, 2014 Teleconference
Approved Meeting Notes	Mark Gustlin	Xilinx
Agenda	Mark Gustlin	Xilinx
Update of Bit multiplexing in 400GbE PMA	Xinyuan Wang Tongtong Wang Wenbin Yang	Huawei
Evaluation of FEC performance with symbol and bit muxing scenarios	Tongtong Wang Xinyuan Wang Wenbin Yang	Huawei
PCS/PMA Architecture and OTN Support Proposal	Steve Trowbridge	ALU

Last Update: 25-Apr 2014

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